Prosecution Insights
Last updated: April 19, 2026
Application No. 18/316,165

LATERAL SEMICONDUCTOR DEVICE COMPRISING UNIT CELLS WITH HEXAGON CONTOURS

Non-Final OA §102§103
Filed
May 11, 2023
Examiner
TRAN, DZUNG
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
846 granted / 1018 resolved
+15.1% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
87 currently pending
Career history
1105
Total Applications
across all art units

Statute-Specific Performance

§101
4.2%
-35.8% vs TC avg
§103
65.0%
+25.0% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
10.8%
-29.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1018 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Status of the Claims Applicant’s election, without traverse, of Specie 1 (Fig. 5), claims 1-7, 9 and 14-15 in the reply filed on September 18th, 2025 is acknowledged. Non-elected invention and species, claims 8, 10-13 and 16-20 have been withdrawn from consideration. Claims 3-5 and 7 belong to other Species have been withdraw by examiner. Claims 1-20 are pending. Action on merits of Species 1, claims 1-2, 6, 9 and 14-15 as follows. Information Disclosure Statement The information disclosure statements (IDSs) submitted on February 19th, 2024; February 20th, 2025; June 10th, 2025 have been considered by the examiner. Drawings The drawings filed on 05/11/2023 are objected. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features: “an isolation layer positioned between the first metallization layer and the second metallization layer, the connection between the second portion of the second metallization layer and the second portion of the first metallization layer being formed by a via extending through the isolation layer” as recited in claim 9, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. 35 USC § 112(f)/sixth paragraph CLAIM INTERPRETATION The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “at least two metallization layers being configured to receive electrical currents from the plurality of first, second and third terminals …;” as recited in claim 1. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action. For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1 and 15 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Shinohara (US 2019/0006464, hereinafter as Shino ‘464). Regarding Claim 1, Shino ‘464 teaches a semiconductor device, comprising: a die layer (Fig. 1, (14); [0018]) comprising a main surface; a plurality of first terminals (16 and 22; [0018]) mounted on the main surface of the die layer, the first terminals forming a grid of unit cells with hexagon contours (Fig. 2, (48); [0022]) arranged side-by-side across the main surface of the die layer; a plurality of second terminals (20a/20b; [0019]) mounted on the main surface of the die layer, each second terminal forming a hexagon contour (Fig. 2, (50a-c); [0021]) arranged within a unit cell of a respective first terminal, a gap being provided between the second terminal and the first terminal; a plurality of third terminals (18; [0018]) mounted on the main surface of the die layer, each third terminal being formed as a hexagon contour (Fig. 2, (46); [0022]) and arranged within the hexagon contour of a respective second terminal, there being a second gap provided between the third terminal and the second terminal; and at least two metallization layers (M1-M3) arranged over the plurality of first, second and third terminals, the at least two metallization layers being configured to receive electrical currents from the plurality of first, second and third terminals (see Fig. 1). Regarding Claim 15, Shino ‘464 teaches a GaN High Electron Mobility Transistor (HEMT) device (see para. [0032]-[0033]). PNG media_image1.png 328 460 media_image1.png Greyscale PNG media_image2.png 372 388 media_image2.png Greyscale Figs. 1 and 2 (Shino ‘464) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Shino ‘464 as applied to claim 1 above, and further in view of Chen (US 2016/0111501, hereinafter as Chen ‘501). Regarding Claim 2, Shino ‘464 teaches the first metallization layer (M1) comprising a first portion, a second portion and a third portion each separated from one another and arranged as follows: the first portion of the first metallization layer (26; [0019]) covering at least a portion of each first terminal (16) and electrically connected to the plurality of first terminals (16) to receive electrical currents from the plurality of first terminals; and the third portion of the first metallization layer (26; [0019]) covering at least a portion of each third terminal (18) and electrically connected to the plurality of third terminals (18) to receive electrical currents from the plurality of third terminals. Thus, Shino ‘464 is shown to teach all the features of the claim with the exception of explicitly the features: “the second portion of the first metallization layer covering at least a portion of each second terminal and electrically connected to the plurality of second terminals to receive electrical currents from the plurality of second terminals”. Chen ‘501 teaches the second portion of the first metallization layer (Fig. 1A, (132); [0022]) covering at least a portion of each second terminal (Fig. 1A, (124); [0022]) and electrically connected to the plurality of second terminals (124) to receive electrical currents from the plurality of second terminals. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Shino ‘464 by having the second portion of the first metallization layer (26; [0019]) covering at least a portion of each second terminal and electrically connected to the plurality of second terminals to receive electrical currents from the plurality of second terminals for the purpose of improving semiconductor structure (see para. [0012]) as suggested by Chen ‘501. Regarding Claim 6, Chen ‘501 teaches the first metallization layer (132) comprises a first portion and a second portion which are separated from each other; the first portion of the first metallization layer (132) covers at least a portion of the plurality of first terminals (118; [0022]) to receive electrical currents from the first terminals; and the second portion of the first metallization layer (132) covers at least a portion of the plurality of second terminals (124) to receive electrical currents from the second terminals. Regarding Claim 9, Chen ‘501 teaches an isolation layer (Fig. 1A, (134); [0022]) positioned between the first metallization layer (132) and the second metallization layer (140; [0022]), the connection between the second portion of the second metallization layer and the second portion of the first metallization layer being formed by a via (138; [0022]) extending through the isolation layer. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Shino ‘464 as applied to claim 1 above, and further in view of Tanimoto (US 2014/0353736, hereinafter as Tani ‘736). Regarding Claim 14, Shino ‘464 teaches one of the hexagon contours of the plurality of first terminals, the hexagon contours of the plurality of second terminals or the hexagons of the plurality of third terminals (see Fig. 2). Thus, Shino ‘464 is shown to teach all the features of the claim with the exception of explicitly the features: “cut corners or rounded corners”. Tani ‘736 teaches a cut corners hexagon contour (Fig. 6, (31c); [0060]). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Shino ‘464 by having the cut corners hexagon contours in order to ensure the good conduction between the adjacent source electrodes as suggested by Shino ‘464. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices: Sheridan et al. (US 2018/0076310 A1) Matsumiya et al. (US 2009/0026506 A1) Chen (US 2006/0267110 A1) Laws (US 2004/0222494 A1) Masuda et al. (US 2003/0136984 A1) For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DZUNG TRAN/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 11, 2023
Application Filed
Nov 10, 2025
Non-Final Rejection — §102, §103
Feb 17, 2026
Response after Non-Final Action
Feb 17, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+5.4%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 1018 resolved cases by this examiner. Grant probability derived from career allow rate.

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