Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-7, 9 and 14-15 in the reply filed on April 20th, 2026 are acknowledged. Claims 1and 9 have been amended. Claims 8, 10-13 and 16-20 have been withdrawn from consideration. Claims 3-5 and 7 belong to other Species have been withdraw by examiner. Claims 1-20 are pending.
Action on merits of claims 1-2, 6, 9 and 14-15 as follows.
Drawings
The drawings filed on 02/17/2026 are accepted.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shinohara (US 2019/0006464, hereinafter as Shino ‘464) in view of Tanimoto (US 2014/0353736, hereinafter as Tani ‘736).
Regarding Claim 1, Shino ‘464 teaches a semiconductor device, comprising:
a die layer (Fig. 1, (14); [0018]) comprising a main surface;
a plurality of first terminals (16 and 22; [0018]) mounted on the main surface of the die layer, the first terminals forming a grid of unit cells with hexagon contours (Fig. 2, (48); [0022]) arranged side-by-side across the main surface of the die layer;
a plurality of second terminals (20a/20b; [0019]) mounted on the main surface of the die layer, each second terminal arranged within a unit cell of a respective first terminal, a gap being provided between the second terminal and the first terminal;
a plurality of third terminals (18; [0018]) mounted on the main surface of the die layer, each third terminal being (Fig. 2, (46); [0022]) and arranged within the hexagon contour of a respective second terminal, there being a second gap provided between the third terminal and the second terminal; and
at least two metallization layers (M1-M3) arranged over the plurality of first, second and third terminals to receive electrical currents from the plurality of first, second and third terminals (see Fig. 1).
Thus, Shino ‘464 is shown to teach all the features of the claim with the exception of explicitly the features: “each second terminal forming a hexagon contour; and each third terminal being formed as a hexagon contour”.
Tani ‘736 teaches each second terminal (gate electrode, Fig. 6, (32); [0061]) forming a hexagon contour; and each third terminal (drain electrode, Fig. 6, (33); [0061]) being formed as a hexagon contour.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Shino ‘464 by having each second terminal forming a hexagon contour; and each third terminal being formed as a hexagon contour in order to maximize the channel area, while keeping a low resistance of the wiring of the source electrode, thereby producing the miniaturized field-effect transistor with the high maximum current (see para. [0063]-[0064]) as suggested by Tani ‘736.
Regarding Claim 15, Shino ‘464 teaches a GaN High Electron Mobility Transistor (HEMT) device (see para. [0032]-[0033]).
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Figs. 1 and 2 (Shino ‘464)
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Fig. 6 (Tani ‘736)
Claims 2, 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Shino ‘464 and Tani ‘736 as applied to claim 1 above, and further in view of Chen (US 2016/0111501, hereinafter as Chen ‘501).
Regarding Claim 2, Shino ‘464 teaches the first metallization layer (M1) comprising a first portion, a second portion and a third portion each separated from one another and arranged as follows:
the first portion of the first metallization layer (26; [0019]) covering at least a portion of each first terminal (16) and electrically connected to the plurality of first terminals (16) to receive electrical currents from the plurality of first terminals; and
the third portion of the first metallization layer (26; [0019]) covering at least a portion of each third terminal (18) and electrically connected to the plurality of third terminals (18) to receive electrical currents from the plurality of third terminals.
Thus, Shino ‘464 and Tani ‘736 are shown to teach all the features of the claim with the exception of explicitly the features: “the second portion of the first metallization layer covering at least a portion of each second terminal and electrically connected to the plurality of second terminals to receive electrical currents from the plurality of second terminals”.
Chen ‘501 teaches the second portion of the first metallization layer (Fig. 1A, (132); [0022]) covering at least a portion of each second terminal (Fig. 1A, (124); [0022]) and electrically connected to the plurality of second terminals (124) to receive electrical currents from the plurality of second terminals.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Shino ‘464 and Tani ‘736 by having the second portion of the first metallization layer (26; [0019]) covering at least a portion of each second terminal and electrically connected to the plurality of second terminals to receive electrical currents from the plurality of second terminals for the purpose of improving semiconductor structure (see para. [0012]) as suggested by Chen ‘501.
Regarding Claim 6, Chen ‘501 teaches the first metallization layer (132) comprises a first portion and a second portion which are separated from each other; the first portion of the first metallization layer (132) covers at least a portion of the plurality of first terminals (118; [0022]) to receive electrical currents from the first terminals; and the second portion of the first metallization layer (132) covers at least a portion of the plurality of second terminals (124) to receive electrical currents from the second terminals.
Regarding Claim 9, Chen ‘501 teaches an isolation layer (Fig. 1A, (134); [0022]) positioned between the first metallization layer (132) and the second metallization layer (140; [0022]), a connection between the second portion of the second metallization layer and the second portion of the first metallization layer being formed by a via (138; [0022]) extending through the isolation layer.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Shino ‘464 and Tani ‘736 as applied to claim 1 above, and further in view of Tanimoto (US 2014/0353736, hereinafter as Tani ‘736).
Regarding Claim 14, Shino ‘464 teaches one of the hexagon contours of the plurality of first terminals, the hexagon contours of the plurality of second terminals or the hexagons of the plurality of third terminals (see Fig. 2).
Thus, Shino ‘464 and Tani ‘736 are shown to teach all the features of the claim with the exception of explicitly the features: “cut corners or rounded corners”.
Tani ‘736 teaches a cut corners hexagon contour (Fig. 6, (31c); [0060]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Shino ‘464 and Tani ‘736 by having the cut corners hexagon contours in order to ensure the good conduction between the adjacent source electrodes as suggested by Shino ‘464.
Response to Arguments
Applicant’s arguments with respect to claims 1-7, 9 and 14-15, filed on April 20th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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