DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner acknowledges that in the reply filed 1/23/2026, claim 10 was cancelled.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-9) in the reply filed on 1/23/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of:
Claim 2, step S5, where a thermal oxide is formed to perform rounding and plasma damage repair and then an oxide is grown on the sidewalls of the trenches and then the oxide is processed through wet etching;
Claim 5, where there is a thickness remaining of an oxide layer formed in step S5 after a wet etching step formed prior to the silicon nitride layer forming step of step S6;
Claim 6, step S17, specifically where the metal and nitride are deposited and a silicide layer is formed;
must be shown or the feature(s) canceled from the claim(s). It is unclear where the silicide layer is to be formed and if the metal and nitride are meant to be two layers or one. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities: in [0001], line 2, “semicondutor” should be amended to read –semiconductor–.
Appropriate correction is required.
Claim Objections
Claim 2 is objected to because of the following informalities: in line 9, "on the mask" should be amended to read -in the mask-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 10, "a pattern" should be amended to read -wherein a pattern-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 15, "on the mask" should be amended to read -in the mask-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 20, "on each of the one or more" should be amended to read -in each of the one or more-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 31, “still retained" should be amended to read -retained-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 31, "until the" should be amended to read -while the-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 33, "the wet etching" should be amended to read -wet etching-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 36, "the pentavalent" should be amended to read -pentavalent-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 37, "the trivalent" should be amended to read -trivalent-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 43, "the trivalent" should be amended to read -trivalent-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 44, "the pentavalent" should be amended to read -pentavalent-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 47, "the pentavalent" should be amended to read -pentavalent-. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: in line 47, "the trivalent" should be amended to read -trivalent-. Appropriate correction is required.
Claim 4 is objected to because of the following informalities: in line 1, "step 12" should be amended to read -step S12-. Appropriate correction is required.
Claim 6 is objected to because of the following informalities: in line 5, "the photoetching" should be amended to read -photoetching-. Appropriate correction is required.
Claim 6 is objected to because of the following informalities: in line 14, "trough" should be amended to read -through-. Appropriate correction is required.
Claim 7 is objected to because of the following informalities: in line 2, "the polarity" should be amended to read -a polarity-. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: in line 4, ". Appropriate correction is required.
Claim 8 is objected to because of the following informalities: in lines 4-5, "a photoetching" should be amended to read -photoetching-. Appropriate correction is required.
Claim 9 is objected to because of the following informalities: in lines 3-4, "a photoetching" should be amended to read -photoetching-. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 2, step S1, “performing chemical vapor deposition on an upper surface of a silicon substrate with one or more epitaxial layers” is unclear as one is not sure if the silicon substrate has the one or more epitaxial layers formed on it before the chemical vapor deposition step, if the chemical vapor deposition is used to form some unmentioned layer on the silicon substate and then the one or more epitaxial layers are formed thereon, or if the chemical vapor deposition step is meant to form the one or more epitaxial layers on the substrate. Only in view of the specification is it apparent that the chemical vapor deposition is used to form the one or more epitaxial layers (see [0042]). Claims 3-7 inherit the deficiencies of claim 2. Appropriate correction is required.
In claim 2, step S1, “the one or more epitaxial layers is doped with trivalent elements and pentavalent elements.” It is unclear if both elements are meant to be present (and how the one or more epitaxial layers would operate if both types of elements are present) or if only one of the elements is present. Only in view of the specification is it apparent that only one of the element types is present (trivalent or pentavalent) in the one or more epitaxial layers (see [0042], sentence 3). Claims 3-7 inherit the deficiencies of claim 2. Appropriate correction is required.
In claim 2, step S4, the limitation “forming a pattern of the circuit on the mask” is unclear if the circuit in this step is the same as or different from that of step C in claim 1 and if the pattern in step S4 is the same as that of S3. In view of the specification, it is apparent that the circuit in step S4 is not the same circuit as in step C (see [0044]-[0045]) and should not be referred to as “the circuit” but as a different identifier/element name. The pattern of the circuit in step S4 is the same pattern as that of step S3, just referred to by a different name (see [0045], sentence 1). The pattern of the circuit of step S4, therefore, is interpreted to be the pattern of the cellular gate trench, the pattern of the source trench, and the pattern of the gate interconnection of step S3. Claims 3-7 inherit the deficiencies of claim 2. Appropriate correction is required.
In claim 2, step S8, the limitation “growing a gate oxide layer through the thermal oxidation method” is unclear as to whether this thermal oxidation method is the same as or different from that of step S5. As they are performed at different times, it is interpreted that it is a separate thermal oxidation step and should be identified as such and not with the article “the”. Claims 3-7 inherit the deficiencies of claim 2. Appropriate correction is required.
In claim 2, step S10, the limitation “the dry etching” is unclear as to whether this dry etching is the same as or different from that of step S4. As they are performed at different times, it is interpreted that it is a separate dry etching step and should be identified as such and not with the article “the”. Claims 3-7 inherit the deficiencies of claim 2. Appropriate correction is required.
In claim 2, step S11, the limitation “the ion implantation” is unclear as to whether this ion implantation is the same as or different from that of step S9. As they are performed at different times, it is interpreted that it is a separate ion implantation step and should be identified as such and not with the article “the”. Claims 3-7 inherit the deficiencies of claim 2. Appropriate correction is required.
In claim 2, step S12, the limitation “the ion implantation” is unclear as to whether this ion implantation is the same as or different from that of steps S9 and S11. As they are all performed at different times, it is interpreted that the implantation of step S12 is a separate ion implantation step and should be identified as such and not with the article “the”. Claims 3-7 inherit the deficiencies of claim 2. Appropriate correction is required.
In claim 5, lines 2-3, it is claimed that “the oxide layer in the step S5 is 10-100 nm” and that a thickness of “the oxide layer after being processed by the wet etching is 20 nm.” It is unclear how if the oxide layer of step S5 is processed by wet etching, which means that it is etched by the wet etching, could be 20 nm when the range includes thicknesses equal to and less than 20 nm prior to the wet etching. This would imply that either the wet etching doesn’t occur, even though it has been claimed to in step S5, or that the thickness after the etching isn’t 20 nm if the original thickness of the oxide prior to the wet etching is equal to or less than 20 nm. Examiner interprets that the oxide layer of step S5 must be greater than 20 nm prior to etching to become 20 nm after etching. Appropriate correction is required.
In claim 6, step S14, the limitation “the photoresist” is unclear as to whether this photoresist is the same as or different from that of step S2. As they are provided at different times, it is interpreted that the photoresist of step S14 is a separate photoresist and should be identified as such and not with the article “the”. Claim 7 inherits the deficiencies of claim 6. Appropriate correction is required.
In claim 6, step S15, the limitation “the dry etching” is unclear as to whether this dry etching is the same as or different from that of step S4. As they are performed at different times, it is interpreted that it is a separate dry etching step and should be identified as such and not with the article “the”. Claim 7 inherits the deficiencies of claim 6. Appropriate correction is required.
In claim 6, step S16, the limitation “etching silicon nitride in a source region trench” is unclear as no step of forming a source region trench nor a step of forming silicon nitride in the source region trench has been claimed. Examiner interprets that the silicon nitride and source region trench of step S16 are the silicon nitride thin film and the source trench of step S6 in claim 2. This is consistent with the specification in Figs. 5, 15, and 16. Claim 7 inherits the deficiencies of claim 6. Appropriate correction is required.
In claim 6, step S17, the limitation “the source region trench” is unclear as to where that is formed. In view of the interpretation of claim 6, step S16 in the preceding paragraph, Examiner interprets that the source region trench is the source trench of step S6 in claim 2 and step S17 of claim 6. Claim 7 inherits the deficiencies of claim 6. Appropriate correction is required.
In claim 6, step S18, the limitation “the dry etching” is unclear as to whether this dry etching is the same as or different from that of step S4 or S15. As they are all performed at different times, it is interpreted that this is a separate dry etching step and should be identified as such and not with the article “the”. Claim 7 inherits the deficiencies of claim 6. Appropriate correction is required.
The term “high concentration” in claim 6, step S17 is a relative term which renders the claim indefinite. The term “high concentration” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “high concentration” needs to be compared against the concentration of another region or have a numerical value or range to be properly established. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lui et al (US 2018/0097078 and Lui hereinafter) in view of Chang et al (US 2013/0228860 and Chang hereinafter) in view of Yilmaz (US 2019/0273157 and Yilmaz hereinafter).
Lui discloses a manufacturing method of a trench type power device (Figs. 1A-1T), comprising: step A, preparing a cellular structure (Figs. 1A-1N; steps of forming the trenches and up to forming the ILD to define contact openings; [0009]-[0013]); step B, preparing contact holes and tungsten bolts (Figs. 1O-1T; contact holes 106 and tungsten bolts 128; [0014]-[0016]).
Lui fails to expressly disclose step C, performing etching to form a circuit. Lui discloses in Fig. 1T forming an electrode 130, but fails to expressly disclose etching it.
Chang discloses in Figs. 31AA’-31LL’ and [0066] a method of forming a trench gate transistor with an electrode 3100 thereon and further comprises step C, performing etching to form a circuit (Figs. 32AA’-32LL’; 3100 is patterned to form 3234, 3235, 3256, and 3278 and the structure shown is the circuit; [0066]-[0067]).
Given the teachings of Chang, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lui by employing the well-known or conventional features of trench gate transistor fabrication, such as displayed by Chang, by employing an etching step to pattern the electrode formed over the gate and source trenches in order to provide separated conductive paths to control the source and gate ([0067]).
Lui in view of Chang fail to expressly disclose step D, depositing a passivation layer and etching the passivation layer.
Yilmaz discloses in Fig. 1A and [0053] a method of forming a trench gate transistor that comprises step D, depositing a passivation layer (128; [0053]) and etching the passivation layer (Fig. 4L; etch passivation layer 128 to open pad areas; [0092] and [0095]).
Given the teachings of Yilmaz, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lui in view of Chang by employing the well-known or conventional features of trench gate transistor fabrication, such as displayed by Yilmaz, by employing a passivation layer that is later etched on the source and gate electrode contacts in order to allow for selective pad formation to the source and gate electrode contact layers and to isolate other areas where no source or gate electrode contact pad location is desired to allow for external connections to the circuit ([0095]).
Claims 2-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lui in view of Chang in view of Yilmaz as applied to claim 1 above, and further in view of Wang et al (CN 109979932 and Wang hereinafter) in view of Ma et al (CN 104022043 and Ma hereinafter; a machine translation is used as an English language equivalent) in view of Kanazawa (JP 2011-216651 and Kanazawa hereinafter; a machine translation is used as an English language equivalent).
As to claims 2-4 and 6-9: Lui combined with Chang and Yilmaz discloses wherein the step A specifically comprises: step S1, forming on an upper surface of a silicon substrate (Fig. 1A; Si wafer; [0009]) with one or more epitaxial layers (epi layer grown on Si wafer the combination referred to as 102; [0009]), where each of the one or more epitaxial layers (epi portion of 102) is doped with trivalent elements and pentavalent elements (the epi layer grown can be n-type (pentavalent elements used implicitly)); step S2, depositing a mask (Fig. 1A; comprising hardmask 104 and a photoresist not shown; [0009]) on an upper surface of each of the one or more epitaxial layers (epi portion of 102), where a component of the mask is a photoresist or a multi-layer combination structure composed of a photoresist (photoresist not shown) and an insulator mask (104); step S3, defining a pattern of a gate trench (Figs. 1B and 1C; wider area patterns 108; [0009]) and a pattern of a source trench (narrower area patterns 106) on the mask ([0009]), where the gate trench (108) comprises a cellular gate trench (108), a pattern of the cellular gate trench (108), the pattern of the source trench (106), are sequentially arranged (as shown, the first cellular gate trench 108 and the second source trench are sequentially arranged), and the critical dimension (width) of the cellular gate trench (108) is greater than a critical dimension (width) of the source trench (as shown this is the case; [0009]); step S4, forming a pattern of the circuit on the mask (the pattern shown in Fig. 1B is the pattern of the circuit; [0009]), and then forming the pattern of the circuit on each of the one or more epitaxial layers (epi portion of 102) through etching to obtain a depth of the cellular gate trench greater (Fig. 1C; 108; [0009]) than a depth of the source trench (106 has a shallower depth than 108; [0009]); step s5, growing an oxide layer (Fig. 1D; 110; [0009]) on each of side walls of the cellular gate trench (108), the source trench (106); step S6, growing a nitride thin film (Fig. 1E; 112; [0010]), where the nitride thin film (112) grows on a bottom surface of the gate trench (108) and fills the source trench (106); step S7, etching the nitride thin film (Fig. 1F; [0010]), where the nitride thin film (112a) is still retained in the source trench (106) until the nitride thin film (112) in the gate trench (108) is completely etched ([0010]); step S8, removing a natural oxide layer (Fig. 1G; 110 is interpreted to be a natural oxide as it is grown from the surface of the epi layer 102; [0010]) in the gate trench (108), and growing a gate oxide layer (Fig. 1I; 114; [0011]); step S9, forming polysilicon (Fig. 1J; 116; [0011]) for filling the gate trench (108) with the polysilicon (116) to form a gate ([0011]), doping the conductive elements in a deposition process of the polysilicon (in-situ doped; [0011]) or doping the trivalent elements through ion implantation after the gate is formed; step S10, removing a part of the polysilicon (Fig. 1J; a topmost part of the polysilicon layer 116 is removed by etching, which is higher than the bottom of the epi portion of 102; [0011]) higher than the one or more epitaxial layers (epi portion of 102); step S11, doping a first impurity (Fig. 1K; opposite to that of the epi layer and substrate 102; [0012]) into the upper surface of each of the one or more epitaxial layers (epi portion of 102) through the ion implantation (body implantation; [0012]) to obtain a body region (118; [0012]), activating the first impurity in the body region through a thermal process (Fig. 1L; heat; [0012]), where the first impurity comprises the trivalent elements or the pentavalent elements (boron and phosphorus and arsenic are trivalent or pentavalent elements; [0012]); and step S12, doping a second impurity (Fig. 1M; [0013]) into an upper surface of the body region (118) through the ion implantation (source implantation; [0013]) to obtain a source region (120; [0013]), where the second impurity implanted by the ion implantation is the pentavalent elements or the trivalent elements (boron and phosphorus and arsenic are trivalent or pentavalent elements; [0013]), so as to finally obtain the cellular structure (Fig. 1N; [0013]); [claim 3] wherein in the step S1, the step S9, the step S11, and the step S12, the trivalent elements comprise boron element, and the pentavalent elements comprises arsenic element and phosphorus element (boron, arsenic, and phosphorus can be used to dope semiconductor materials; [0012]); [claim 4] wherein a polarity of the first impurity doped through the ion implantation in the step S11 is opposite to a polarity of the trivalent elements and the pentavalent elements doped in each of the one or more epitaxial layers in the step S1 (body implant is of opposite conductivity type (polarity) to that of the substrate and epi layer 102; [0012]), and a polarity of the second impurity doped by the ion implantation in the step 12 is same as the polarity of the trivalent elements and the pentavalent elements doped in each of the one or more epitaxial layers in the step S1 (the source region implant is of the same type conductivity type (polarity) as that of the substrate and epi layer 102; [0012]-[0013]); [claim 6] wherein the step B specifically comprises: step S13, forming a silicon dioxide dielectric layer (Fig. 1O; 122 is BPSG, which comprises silicon dioxide; [0014]); step S14, configuring the photoresist (Fig. 1P; contact photoresist (not shown); [0015]) to define a pattern of a source region trench contact hole (opening over 106; [0015]) through the photoetching technology (inherent to the process), where the pattern of the source region trench contact hole is located above the source trench (as shown in Fig. 1P); step S15, etching the silicon dioxide dielectric layer (Fig. 1P; [0015]) through the etching to obtain the source region trench contact hole (above 106); step S16, etching silicon nitride (Figs. 1P and 1Q; 112a; [0015]) in a source region trench (106); step S17, doping a third impurity (Fig. 1T; contact regions 124; [0015]) having high concentration to a bottom of the source region trench (106), forming an ohmic contact (comprising 126 and 128) of the source region trench contact hole (106), and activating the third impurity (inherently performed to allow for a good contact to be made); depositing metal and nitride as a protective layer (Fig. 1T; 126 is TiN; [0016]), where the metal comprises one or more of titanium, cobalt, and tantalum (Titanium; [0016]); and step S18, depositing metal tungsten (Fig. 1T; 128 is Tungsten; [0016]) through a tungsten bolt technology (technology used is interpreted to be a tungsten bolt technology as that is what is produced), removing a part of the metal tungsten other than each of the contact holes (Fig. 1T; etch back of tungsten; [0016]), and forming each of the tungsten bolts (Fig. 1T; 128; [0016]) in each of the contact holes (106); [claim 7] wherein the polarity of the second impurity doped through the ion implantation in the step S12 is same as a polarity of the third impurity doped through the ion implantation in the step S17 (standard process as it is known in the art implies this limitation; [0016]); [claim 8] wherein the step C specifically comprises: step S19, respectively depositing aluminum-copper compound (Fig. 1T; 130 is AlCu; [0016]) above the tungsten bolts (128).
Liu combined with Chang combined with Yilmaz fails to expressly disclose where the pattern of the gate trench also comprises a gate interconnection trench, where the pattern of the cellular gate trench, the source trench, and a pattern of the gate interconnection trench are sequentially arranged, a critical dimension of the gate interconnection trench is greater than a critical dimension of the cellular gate trench, where a depth of the gate interconnection trench greater than a depth of the cellular gate trench, in step S6, where the oxide layer is formed on the sidewalls of the gate interconnection trench; [claim 6] step S13, the silicon dioxide is formed through chemical vapor deposition; in step S14, where the photoresist defines a pattern of a gate interconnection region contact hole through photoetching technology, and the pattern of the gate interconnection region contact hole is located above the gate interconnection trench; step S17, where the third impurity is activated trough rapid thermal annealing, forming silicide through rapid thermal degradation; [claim 8] then performing the etching through a photoetching technology and etching to form the circuit.
Chang discloses a method of forming a trench gate transistor where the pattern of the gate trench (Figs. 7AA’-7LL’ and 8AA’-8LL’; comprises 704 and 708; [0037]) also comprises a gate interconnection trench (708; [0037]), where the pattern of the cellular gate trench (704), the source trench (706; [0037]), and a pattern of the gate interconnection trench (708; [0037]) are sequentially arranged (Fig. 1D; AA’ is where 704 is found, BB’ is where 706 is found, and LL’ is where 708 is found and they are in that order from left to right; [0033]), a critical dimension (width) of the gate interconnection trench (708) is greater than a critical dimension (width) of the cellular gate trench (as shown in Figs. 7AA’ and 7LL’, 704 has a smaller width than that of 708; [0036]-[0040]), where a depth of the gate interconnection trench greater than a depth of the cellular gate trench (as discussed in Liu ([0009]) and Chang ([0036]), the wider the opening, the deeper the trench); in step S6, where the oxide layer is formed on the sidewalls of the gate interconnection trench (when 708 is incorporated into Liu, the oxide 110 of Liu will be formed in the gate interconnection trenches 708 as well); [claim 6] step S13, the silicon dioxide is formed through chemical vapor deposition (silicon dioxide containing materials can be formed through CVD; [0058]); in step S14, where the photoresist defines (Fig. 28AA’-28LL’; a photoresist 2800 is formed over all of the trenches; [0061]) a pattern of a gate interconnection region contact hole (2802 for gate interconnection regions and 2804 for source contact region; [0062]) through photoetching technology (inherent to the process described), and the pattern of the gate interconnection region contact hole (2802) is located above the gate interconnection trench (708); step S17, where the third impurity is activated trough rapid thermal annealing (Fig. 29AA’-29LL’; third impurity is in the contact implant region and activated through RTP; [0063]), forming silicide through rapid thermal degradation (Fig. 30AA’-30LL’; silicide formed through RTP, which is interpreted to be rapid thermal degradation; [0064]); [claim 8] then performing the etching through a photoetching technology (Fig. 31AA’-31LL’; as a photoresist 3101 is used to etch 3100, inherently photoetching technology is used; [0066]-[0067]) and etching to form the circuit (Figs. 32AA’-32LL’; etching to form separate regions from 3100; [0067]).
Given the teachings of Chang, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Liu by employing the well-known or conventional features of trench gate transistor fabrication, such as displayed by Chang, by employing a third gate type that is a gate interconnection trench that is wider than the cellular gate trench and the source trench and formed such that the cellular gate trench, the source trench, and the gate interconnection trench are formed in that order from left to right, and the gate interconnection trench is deeper than the other two trench types in order to provide a means to connect the cellular gate trench to the gate terminal (through the gate interconnection trench) to access/activate the transistor gate, see [0023]-[0026] and [0069] and the choice of widths reduces void formation, see [0029], using a well-known technique of providing an oxide of good quality using CVD ([0058]), using RTP to activate the implanted dopants to lower the contact resistance of the region, forming a silicide using a rapid thermal anneal to lower resistance to the contact region.
Liu in view of Chang fails to expressly disclose [claim 9] wherein the step D specifically comprises: step S20, depositing the passivation layer and etching the passivation layer through a photoetching technology, where the passivation layer comprises silicon nitride or silicon dioxide.
Yilmaz discloses in Fig. 1A and [0053] a method of forming a trench gate transistor that comprises wherein the step D specifically comprises: step S20, depositing the passivation layer (128; [0053]) and etching the passivation layer through a photoetching technology (Fig. 4L; etch passivation layer 128 to open pad areas can be performed using the techniques of Fig. 4B-4L, such as using a photoresist and photoetching technology to etch an opening as in Fig. 4E; [0089] and [0095]), where the passivation layer (128) comprises silicon nitride or silicon dioxide (SiO2 can be used as a dielectric layer to isolate electrical features; [0052] and [0055]).
Given the teachings of Yilmaz, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lui in view of Chang by employing the well-known or conventional features of trench gate transistor fabrication, such as displayed by Yilmaz, by employing a passivation layer that is later etched on the source and gate electrode contacts in order to allow for selective pad formation to the source and gate electrode contact layers and to isolate other areas where no source or gate electrode contact pad location is desired to allow for external connections to the circuit using a passivation layer material (SiO2) that allows for a desired level of isolation ([0095]).
Lui in view of Chang in view of Yilmaz fail to expressly disclose where forming the one or more epitaxial layers in step S1 is through performing chemical vapor deposition.
Wang discloses a method of forming a semiconductor device with a starting substrate 301 where forming the one or more epitaxial layers (epitaxial layer 302) in step S1 is through performing chemical vapor deposition (CVD; [0057]).
Given the teachings of Wang, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Liu in view of Chang in view of Yilmaz by employing the well-known or conventional features of epitaxial layer fabrication, such as displayed by Wang, by employing a CVD method to grow the epitaxial layer on the substrate in order to use a method that can flexibly be adjusted to grow the epitaxial layer as desired ([0057]).
Lui in view of Chang in view of Yilmaz in view of Wang fail to expressly disclose where the etching of the epitaxial layers in step S4 is a dry etching, wherein step S5, performing rounding and plasma damage repair on the cellular gate trench, the source trench, and the gate interconnection trench through a thermal oxidation method, growing an oxide layer on each of side walls of the cellular gate trench, the source trench, and the gate interconnection trench, and processing the oxide layer through wet etching; wherein in step S9 the polysilicon is formed through low-pressure chemical vapor deposition and the elements are pentavalent elements, wherein step S10 the polysilicon is removed through chemical mechanical polishing or the dry etching; [claim 6] step S15 where the etching is dry etching to obtain the gate interconnection trench contact hole.
Ma discloses a method of forming a trench gate transistor where the etching of the epitaxial layers (Fig. 1A; epitaxial layer 101b; [0048]) in step S4 is a dry etching (dry plasma etching; [0048]), wherein step S5, performing rounding and plasma damage repair on the cellular gate trench, the source trench, and the gate interconnection trench through a thermal oxidation method (Fig. 1B; a sacrificial oxide layer (not shown) grown by thermal oxidation is formed on the exposed trenches, such as the cellular gate trench, source trench, and gate interconnection trench of Lui in view of Chang in view of Yilmaz in view of Wang, to repair damage, such as plasma damage from plasma etching of the trenches, and to round the bottoms of the trenches; [0049]), and processing the oxide layer through wet etching (Fig. 1F; oxide layers can be removed by wet etching; [0052]); wherein in step S9 the polysilicon (Fig. 1H; 107; [0054]) is formed through low-pressure chemical vapor deposition (LPCVD; [0054]) and the elements are pentavalent elements (the polysilicon is doped, which is through the use of either trivalent or pentavalent elements depending on the device type; [0054]), wherein step S10 the polysilicon is removed through chemical mechanical polishing or the dry etching (Fig. 1I; polysilicon outside of the trenches is removed by dry plasma etching; [0054]); [claim 6] step S15 where the etching is dry etching to obtain the gate interconnection trench contact hole (dry etching can be used to form contact holes in a dielectric; [0062]).
Given the teachings of Ma, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Liu in view of Chang in view of Yilmaz in view of Wang by employing the well-known or conventional features of trench gate transistor fabrication, such as displayed by Ma, by employing a thermally grown sacrificial oxide that is later removed to improve the trench surfaces, using a well-known process to remove a silicon oxide, forming the pentavalent doped polysilicon in order to provide a high conducting material formed using a well-known technique and removing portions of the polysilicon using a well-known method in order to prevent shorts between adjacent conductive features while using a well-known etching technique to form contact holes selectively ([0048]-[0055]).
Liu in view of Chang in view of Yilmaz in view of Wang in view of Ma fail to expressly disclose wherein in step S6 the nitride film is silicon nitride and is grown through low-pressure chemical vapor deposition, where in step S7 the silicon nitride is etched through hot phosphoric acid, wherein in step S8 the natural oxide is removed through the wet etching and where the gate oxide is grown through the thermal oxidation method; [claim 6] step S16 where the silicon nitride is etched through hot phosphoric acid.
Kanazawa discloses a method of making a trench gate transistor wherein in step S6 the nitride film is silicon nitride (well-known to use a silicon nitride as a film with etch selectivity to silicon oxide; [0046]-[0047]) and is grown through low-pressure chemical vapor deposition (LP-CVD; [0047]), where in step S7 the silicon nitride is etched through hot phosphoric acid (silicon nitride can be removed using thermal (hot) phosphoric acid; [0052]), wherein in step S8 the natural oxide is removed through the wet etching (silicon oxide can be removed using a wet etching process; [0019]) and where the gate oxide is grown through the thermal oxidation method (gate oxide can be formed through thermal oxidation; [0012]); [claim 6] step S16 where the silicon nitride is etched through hot phosphoric acid (silicon nitride can be removed using thermal (hot) phosphoric acid; [0052]);
Given the teachings of Kanazawa, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Liu in view of Chang in view of Yilmaz in view of Wang in view of Ma by employing the well-known or conventional features of trench gate transistor fabrication, such as displayed by Kanazawa, by employing a silicon nitride as the sacrificial nitride in the trenches, the silicon nitride is formed through LPCVD, and is removed through hot phosphoric acid in order to provide a layer with etch selectivity to silicon oxide that has good trench filling capability and can be completely removed by the acid treatment ([0047] and [0052]) and using well-known techniques to form a gate material of low dielectric constant of good quality and use a well-known technique to selectively remove a natural oxide.
As to [claim 6] in step S17, where the metal and nitride are formed through a physical vapor deposition technology, and S18, where the etch back of the tungsten is done through the dry etching, PVD is a well-known technique in the prior art for forming layers of good quality and dry etching has been shown in the cited documents in this Office action that dry etching is a well-known technique to remove material. Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to use a well-known and established technique for providing a layer or removing a layer in a semiconductor device, such as PVD or dry etching, respectively, in order to provide a layer of good quality or to controllably remove a desired level of material, respectively.
As to [claim 8] where the AlCu is formed though the physical vapor deposition technology, where the etching is dry etching, PVD is a well-known technique in the prior art for forming layers of good quality and dry etching has been shown in the cited documents in this Office action that dry etching is a well-known technique to remove material. Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to use a well-known and established technique for providing a layer or removing a layer in a semiconductor device, such as PVD or dry etching, respectively, in order to provide a layer of good quality or to controllably remove a desired level of material, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/27/2026