DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of embodiment 7 as shown in fig. 2a (claims 1-3, 8-10, 14, 15 readable thereon, claims 4-7, 11-13, 16-20 withdrawn) in the reply filed on 11/10/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-10, 14, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PGPub 2019/0161346; hereinafter “Lee”).
Re claim 1: Lee teaches (e.g. fig. 2) a microelectromechanical component comprising: a support layer (substrate 202 and interconnect layer 204; e.g. paragraph 16); a device layer (MEMS substrate 206; e.g. paragraph 16) on the support layer (202, 204); and a cap layer (capping substrate 106; e.g. paragraph 17) having a top surface (top surface of 106; hereinafter “106TS”) and that is on the device layer (206) opposite to the support layer (202, 204), wherein the support layer (202, 204), the device layer (206) and the cap layer (106) define a first cavity (second sealed cavity C2; e.g. paragraph 14) and a second cavity (first sealed cavity C1; e.g. paragraph 14), wherein the device layer (206) includes a first microelectromechanical device structure (104B) in the first cavity (C2) and a second microelectromechanical device structure (104A) in the second cavity (C1), wherein the cap layer (106) comprises a through-hole (vent 114; e.g. paragraph 14) that extends from the top surface (106T) of the cap layer (106) to the first cavity (C2), and wherein a plug (118) is disposed inside the through-hole (114) to seal the first cavity (C2).
Re claim 2: Lee teaches the microelectromechanical component according to claim 1, wherein the cap layer (106) comprises one or more silicon regions (106 is formed of silicon; therefore the region of 106 around 114 is formed of silicon; e.g. paragraph 50; hereinafter “SR”), and the through-hole (114) is in one of the one or more silicon regions (SR).
Re claim 3: Lee teaches the microelectromechanical component according to claim 2, wherein the cap layer comprises two or more silicon regions (left region of 106 and right region of 106) and one or more insulating regions (lining structure 116 is a dielectric; e.g. paragraph 22) that separate the two or more silicon regions electrically from each other.
Re claim 8: Lee teaches (e.g. fig. 2) a microelectromechanical component comprising: a support layer (substrate 202 and interconnect layer 204; e.g. paragraph 16) that includes a first cavity (second sealed cavity C2; e.g. paragraph 14) and a second cavity (first sealed cavity C1; e.g. paragraph 14) disposed therein; a device layer (MEMS substrate 206; e.g. paragraph 16) on the support layer (202, 204) and including a first microelectromechanical device structure (104B) in the first cavity (C2) and a second microelectromechanical device structure (104A) in the second cavity (C1); a cap layer (capping substrate 106; e.g. paragraph 17) on the device layer (206) opposite to the support layer (202, 204) and including a through-hole (vent 114; e.g. paragraph 14) that extends from an outer surface of the cap layer (106) to the first cavity (C2); and a plug (118) in the through-hole (114) to seal the first cavity (C2).
Re claim 9: Lee teaches the microelectromechanical component according to claim 8, wherein the support layer(202, 204), the device layer (206) and the cap layer (106) collectively define the first cavity (second sealed cavity C2; e.g. paragraph 14) and the second cavity (first sealed cavity C1; e.g. paragraph 14).
Re claim 10: Lee teaches the microelectromechanical component according to claim 8, wherein the cap layer comprises two or more silicon regions (left region of 106 and right region of 106) and one or more insulating regions (lining structure 116 is a dielectric; e.g. paragraph 22) that separate the two or more silicon regions electrically from each other.
Re claim 14: Lee teaches (e.g. fig. 2) a method for manufacturing a microelectromechanical component that includes a support layer (substrate 202 and interconnect layer 204; e.g. paragraph 16), a device layer (MEMS substrate 206; e.g. paragraph 16) and a cap layer (capping substrate 106; e.g. paragraph 17), the method comprising: forming recessed regions (removed portions of 204 and 106 for forming C1, C2) in at least one of the support layer (202, 204), the device layer (206) and in the cap layer (106) to define for delimiting a first cavity (second sealed cavity C2; e.g. paragraph 14) and a second cavity (first sealed cavity C1; e.g. paragraph 14); forming a through-hole (vent 114; e.g. paragraph 14) through the cap layer (106); attaching the cap layer (106) to the device layer (206) in a surrounding first gas atmosphere (first gas pressure P1; e.g. paragraph 27) so that the through-hole (114) overlies the first cavity (C2); changing the surrounding first gas atmosphere (P1) to a surrounding second gas atmosphere (P2) that is different than the surrounding first gas atmosphere (P1); and depositing a layer of plug material (118) on the top surface of the cap layer (106) at least over the through-hole (114) until a plug (118) that seals the through-hole (114) is formed inside the through-hole (114).
Re claim 15: Lee teaches the method according to claim 14, further comprising forming the cap layer (106) to include one or more silicon regions (left region of 106 and right region of 106), and forming the through-hole (114) in one of the one or more silicon regions (right silicon region).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US PGPubs 2012/0299127, 2015/0123217, 2016/0244325, 2016/0130137, 2016/0272486, 2016/0332867, 2016/0355394 all teach structures similar to the reference used above in the rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898