DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 7 and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2018/0090449).
Regarding claim 1, Jeong discloses a semiconductor package, comprising:
a first substrate (112, fig. 1 and paragraph 0020);
a first semiconductor chip on the first substrate (132, figs. 1 and paragraph 0025);
a molding layer on the first substrate and the first semiconductor chip (140, fig. 1 and paragraph 0019), the molding layer having a plurality of recesses (144H, fig. 5F and paragraph 0066);
a plurality of substrate connection terminals on the first substrate and in the plurality of recesses (126, figs. 1 and paragraph 0026); and
a second semiconductor chip on the plurality of substrate connection terminals (136, fig. 1 and paragraph 0026),
wherein the plurality of recesses and the plurality of substrate connection terminals (126, fig. 1) are horizontally spaced apart from the first semiconductor chip (132, fig. 1), and
wherein the molding layer (140, fig. 1) is spaced apart from the second semiconductor chip (136, fig. 1).
wherein the second semiconductor chip (136, fig. 1) is spaced apart in a horizontal direction from the first semiconductor chip (132, fig. 1), and
wherein the molding layer (140, fig. 1) contacts a top surface of the first semiconductor chip (132, fig. 1) and is arranged under a bottom surface of the second semiconductor chip (136, fig. 1).
Regarding claim 2, Jeong further discloses wherein the plurality of recesses are arranged in a two-dimensional array (126, fig. 1 and paragraph 0026, note: fig. 1 is a cross section and only shows 2 of the recesses, however, it is understood to be two-dimensional).
Regarding claim 5, Jeong further discloses wherein the second semiconductor (136, fig. 1) is a part of a stack comprising a plurality of semiconductor chips (paragraph 0026).
Regarding claim 7, Jeong further discloses wherein the first semiconductor chip includes a logic chip, and the second semiconductor chip includes a memory chip (paragraph 0028).
Regarding claim 9, Jeong further discloses wherein the plurality of substrate connection terminals are spaced apart from the molding layer (126, fig. 1).
Regarding claim 10, Jeong further discloses wherein at least portions of the plurality of substrate connection terminals are in contact with the molding layer (126, fig. 1).
Regarding claim 11, Jeong further discloses wherein a thickness of each of the plurality of substrate connection terminals is greater than a thickness of the molding layer (126, fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2018/0090449).
Regarding claim 8, Jeong discloses the semiconductor package of claim 1, as mentioned above. Jeong does not explicitly disclose wherein a portion of the molding layer between the ones of the plurality of substrate connection terminals has a thickness of 50 um to 150 um. Such thickness ranges were well within the practices of semiconductor manufacturing at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Claims 3-4 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2018/0090449) in view of Hwang et al. (US 2017/0243857).
Regarding claims 3-4, Jeong discloses the semiconductor package of claim 1 as mentioned above. Jeong discloses that the second chip (136, fig. 1 and paragraph 0026) is directly connected to the connection terminals (fig. 1). Jeong does not disclose wherein the second chip is connected to a second substrate by connection terminals that is then connected to the first substrate.
However, it is well known in the art of semiconductor package manufacturing that one can substitute stacked chips with stacked packages where the chip is on a separate substrate and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate such known teachings, Hwang figure 1 discloses a chip 110a stacked on a substrate 120 (paragraphs 0026-0030) and in another embodiment, Hwang discloses the package of figure 8, which has the stacked chip 211 on it’s own substrate 212 stacked on a substrate 220 (paragraphs 0087-0091).
Regarding claim 13, Jeong discloses a semiconductor package, comprising a first semiconductor package (fig. 5F) and a second semiconductor package (136, figs. 1, 5G),
wherein the first semiconductor package includes:
a first substrate (112, fig. 1 and paragraph 0020) including a first region (I, fig. 1 and paragraph 0022) and a second region (II, fig. 1 and paragraph 0022) that is horizontally spaced apart from the first region;
a first semiconductor chip mounted on the first region of the first substrate (132, figs. 1 and paragraph 0025);
a plurality of connection terminals between the first substrate and the first semiconductor chip (122, 114A, fig. 1 and paragraph 0020); and
a molding layer on the first substrate and the first semiconductor chip (140, fig. 1 and paragraph 0019),
wherein the second semiconductor package includes:
a plurality of substrate connection terminals on the second region of the first substrate (126, fig. 1 and paragraph 0026);
a second semiconductor chip (136, fig. 1 and paragraph 0026),
wherein the molding layer comprises a plurality of recesses that are arranged in a two-dimensional array on the second region of the first substrate (144H, fig. 5F and paragraph 0066 note: fig. 5F is a cross section and only shows 2 of the recesses, however, it is understood to be two-dimensional), and
wherein the plurality of substrate connection terminals are in respective ones of the plurality of recesses and electrically connect the first semiconductor package to the second semiconductor package (126, figs. 1 and paragraph 0026),
wherein the second semiconductor chip (136, fig. 1) is spaced apart in a horizontal direction from the first semiconductor chip (132, fig. 1), and
wherein the molding layer (140, fig. 1) contacts a top surface of the first semiconductor chip (132, fig. 1) and is arranged under a bottom surface of the second semiconductor chip (136, fig. 1).
Jeong discloses that the second semiconductor package is a single chip or a plurality of chips (136, fig. 1 and paragraph 0026). Jeong does not explicitly disclose wherein these chips are on a second substrate that is on the plurality of substrate connection terminals.
However, it is well known in the art of semiconductor package manufacturing that one can substitute stacked chips with stacked packages where the chip is on a separate substrate and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate such known teachings, Hwang figure 1 discloses a chip 110a stacked on a substrate 120 (paragraphs 0026-0030) and in another embodiment, Hwang discloses the package of figure 8, which has the stacked chip 211 on it’s own substrate 212 stacked on a substrate 220 (paragraphs 0087-0091).
Regarding claim 14, Jeong further discloses wherein the molding layer is spaced apart from the second semiconductor package (136, fig. 1).
Regarding claim 15, Jeong further discloses an underfill layer between the first substrate and the first semiconductor chip, the underfill layer on side surfaces of the connection terminals between the first substrate and the first semiconductor chip (140, fig. 1 and paragraph 0035).
Regarding claim 16, Jeong further discloses a plurality of external connection terminals on a bottom surface of the first substrate (114D, fig. 1 and paragraph 0020).
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2018/0090449) in view of Kwon et al. (US 2015/0014862).
Jeong discloses the package of claim 1, as mentioned above. Jeong does not disclose wherein a portion of the molding layer between ones of the plurality of substrate connection terminals has a width that decreases in a direction from bottom to top surfaces of the portion of the molding layer or wherein a width of each of the plurality of substrate connection terminals has a maximum at a center of the at least one of the plurality of substrate connection terminals. However, such inter-mold connection terminals were well known at the time filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate such known teachings see the connection terminals of Kwon (295, figs. 3-4).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 2/26/26