DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 7, 11 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20130069239 A1, Kim‘239).
Regarding independent claim 1, Kim‘239 teaches, “An integrated circuit (fig. 1-18; ¶ [0043] - ¶ [0180]), comprising:
a substrate (186/170, fig. 18);
a stacked silicon die (188) located on the substrate (170);
an oxide layer (148, silicon dioxide) formed directly on the stacked silicon die (188) on an opposite side as the substrate (174); and
a carrier (162/144) over the oxide layer (148)”.
Regarding claim 5, Kim‘239 further teaches, “The integrated circuit of claim 1, further comprising bumps and/or microbumps (196) between the substrate (186/170) and the stacked silicon die (188); and wherein the carrier (162/144) is a silicon carrier (wafer, ¶ [0055])”.
Regarding independent claim 7, Kim‘239 teaches, “An integrated circuit package (fig. 1-18; ¶ [0043] - ¶ [0180]), comprising:
an integrated circuit (fig. 18) that includes:
a stacked silicon die (188); and
an oxide layer (148, silicon dioxide) chemically coupled (CVD, ¶ [0057]) to a back side of the stacked silicon die (188);
a carrier (162/144) attached to the oxide layer (148); and
a substrate (186/170) on a front side of the stacked silicon die (188)”.
Regarding claim 11, Kim‘239 further teaches, “The integrated circuit package of claim 7, wherein the carrier (144) is a silicon carrier (¶ [0055])”.
Regarding claim 14, Kim‘239 further teaches, “The integrated circuit package of claim 7, wherein the stacked silicon die includes two or more 3D stacked silicon dies (188, 680)”.
Regarding claim 15, Kim‘239 further teaches, “The integrated circuit package of claim 7, wherein the stacked silicon die includes multiple silicon dies stacked on an interposer (186, ¶ [0069])”.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20110026232 A1, hereinafter Lin‘232).
Regarding independent claim 1, Lin‘232 teaches, “An integrated circuit (fig. 1-298; ¶ [0077] - ¶ [0831]), comprising:
a substrate (176, fig. 83);
a stacked silicon die (118/72) located on the substrate (176);
an oxide layer (60, ¶ [0118]) formed directly on the stacked silicon die (118/72) on an opposite side as the substrate (176); and
a carrier (11/10) over the oxide layer (60)”.
Regarding independent claim 7, Lin‘232 teaches, “An integrated circuit package (fig. 1-298; ¶ [0077] - ¶ [0831]), comprising:
an integrated circuit (555) that includes:
a stacked silicon die (118/72); and
an oxide layer (60, ¶ [0118]) chemically (CVD, ¶ [0118]) coupled to a back side of the stacked silicon die (118/72);
a carrier (11/10) attached to the oxide layer (60); and
a substrate (176) on a front side of the stacked silicon die (118/72)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 6, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim‘239.
Regarding claim 2, “wherein the oxide layer has a thickness in a range of one to two micrometers”, Kim‘239 teaches, the oxide layer (148, fig. 18). While Kim‘239 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Kim‘239 further teaches, “wherein the substrate (170, wafer, ¶ [0064]) comprises bulk silicon”.
Regarding claim 6, “wherein the oxide layer restricts access to a security asset of the stacked silicon die”, as the applicant’s oxide layer and the carrier of Kim‘239 are made of same materials (Silicon Oxide and Silicon respectively) and the oxide layer located in same relative position between the carrier and the stacked silicon dies, this is naturally recognized that the oxide layer will possess the functionally of restricting access to a security asset of the stacked silicon die. See MPEP § 2114.I.
Regarding claim 8, “wherein the oxide layer has a thickness in a range of one to two micrometers”, Kim‘239 teaches, the oxide layer (148, fig. 18). While Kim‘239 does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Kim‘239 further teaches, “wherein the packaging substrate (170, wafer, ¶ [0064]) comprises bulk silicon”.
Regarding claim 12, “wherein the oxide layer restricts access to a security asset of the stacked silicon die”, as the applicant’s oxide layer and the carrier of Kim‘239 are made of same materials (Silicon Oxide and Silicon respectively) and the oxide layer located in same relative position between the carrier and the stacked silicon dies, this is naturally recognized that the oxide layer will possess the functionally of restricting access to a security asset of the stacked silicon die. See MPEP § 2114.I.
Regarding claim 13, Kim‘239 further teaches, “The integrated circuit package of claim 12, wherein the security asset corresponds to at least one of a root of trust of the stacked silicon die or a die to die interconnect of the stacked silicon die (fig. 18, Kim‘239, die 188 to die 680 interconnect)”.
Claims 3-4, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin‘232 as applied to claim 1/7 above, and further in view of Oliver et al. (US 20180012932 A1, hereinafter Oliver‘932).
Regarding claim 3, Lin‘232 teach all the limitations described in claim 1.
Lin‘232 further teaches, wherein the carrier (11/10) is a glass carrier (¶ [0081]).
But Lin‘232 is silent upon the provision of wherein the carrier having one or more thermal vias formed therein.
However, Oliver‘932 teaches a similar stack device (fig. 8), wherein the glass carrier (81, ¶ [0231]) having one or more thermal vias (811-817) formed therein.
Lin‘232 and Oliver‘932 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin‘232 with the features of Oliver‘932 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lin‘232 and Oliver‘932 to include thermal vias in the glass carrier/substrate according to the teachings of Oliver‘932 with a general motivation of cooling the silicon dies during operation.
Regarding claim 4, Lin‘232 modified with Oliver‘932 further teach, “The integrated circuit of claim 3, wherein the one or more thermal vias (formed in glass carrier 10 in fig. 55 of Lin‘232) are separated from the stacked silicon die (118/72) by glass (62, ¶ [0079]).
Regarding claim 9, Lin‘232 teach all the limitations described in claim 7.
Lin‘232 further teaches, wherein the carrier (11/10) is a glass carrier (¶ [0081]).
But Lin‘232 is silent upon the provision of wherein the carrier having one or more thermal vias formed therein, the integrated circuit further comprising: a thermally conductive material filling at least part of the one or more thermal vias.
However, Oliver‘932 teaches a similar stack device (fig. 8), wherein the glass carrier (81, ¶ [0231]) having one or more thermal vias (811-817) formed therein, the integrated circuit further comprising: a thermally conductive material filling at least part of the one or more thermal vias.
Lin‘232 and Oliver‘932 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin‘232 with the features of Oliver‘932 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lin‘232 and Oliver‘932 to include thermal vias in the glass carrier/substrate according to the teachings of Oliver‘932 with a general motivation of cooling the silicon dies during operation.
Regarding claim 10, Lin‘232 modified with Oliver‘932 further teaches, “The integrated circuit package of claim 9, wherein the one or more thermal vias (811-817, fig. 8, Oliver‘932) do not connect to the stacked silicon die (1850, 1860 etc.)”.
Response to Arguments
Applicant’s arguments with respect to the newly amended claims have been considered but are moot because the arguments do not apply to any of the references being as used in the current rejection.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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