DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/12/2026 has been entered.
Response to Arguments
Applicant’s arguments filed 2/12/2026 with respect to claim(s) 1-20 have been considered but are not found persuasive.
Applicant argues on page 9 that doped region 250 of Lu is not part of a channel region but rather is part of a common source region, and since region 250 is not part of a channel region, it does not extend between a cell contact plug and a source structure as claims 1, 13, 17 now require.
Examiner respectfully disagrees. Paragraph 79 of the originally filed specification states that “the channel layer VSL may be formed of or include a material whose electron mobility is higher than that of polysilicon.” Therefore, the channel layer being taught by elements 228, 251, and doped region 250 would be aligned with the teachings of the instant application. As shown in the updated rejection below, element 250 extends between the cell contact plug 258 and the source structure 244.
Applicant further argues that Lu does not teach the limitations of claim 4 and therefore the rejection of claim 4 is improper because elements 964, 962, 902 is not in Lu.
Examiner has corrected the typographical error that remained from the first non-final rejection and has been updated to appropriately reference the right element numbers of Matsuda.
The rejection has been updated to include the amended portions of the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 6, 8, 9, 11, 13, 14 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US PGPub 2019/0081069; hereinafter “Lu”).
Re claim 1: Lu teaches (e.g. figs. 2 and labeled fig. 2 below) a three-dimensional semiconductor memory device, comprising: a substrate (202); a peripheral circuit structure (peripheral interconnect layer 222; e.g. paragraph 57) on the substrate (202); and a cell array structure (262; e.g. paragraph 71) on the peripheral circuit structure (222), the cell array structure (262) comprising: a cell array region (region of 262 labeled “CAR”); a cell array contact region (region of 262 labeled “CACR”) extended from the cell array region (CAR) in a direction parallel to a top surface of the substrate (202); a stack (alternating conductor/dielectric stack 242; e.g. paragraph 59) that includes interlayer insulating layers (dielectric layer 236; e.g. paragraph 59) and conductive patterns (conductor layer 234; e.g. paragraph 59) alternately stacked with one another; a source structure (244; e.g. paragraph 62) on the stack (242); a vertical structure (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62; hereinafter “VS”) that extends in the stack (242) and is electrically connected to a bottom surface of the source structure (244), and cell contact plugs (word line contacts 258; e.g. paragraph 64) in the cell array contact region (CACR) and connected to the conductive patterns (234), respectively, wherein the vertical structure (VS) comprises a channel layer (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62) that includes first portions (channel 228, epi layer 251; hereinafter “1P”) respectively in vertical channel holes (holes for VS; hereinafter “VCH”) extending in the stack (242), and a second portion (doped region 250; hereinafter “2P”) that extends in a region between the stack (242) and the source structure (244), wherein the second portion (2P) extends between adjacent vertical channels holes (VCH) of the stack (242), wherein the second portion (2P) is in contact with the first portions (1P) within the adjacent vertical channel holes (VCH); wherein the second portion (2P) is in both the cell array region (CAR) and the cell array contact region (CACR), and the second portion (2P) extends between the cell contact plugs (258) and the source structure (244).
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Re claim 2: Lu teaches the semiconductor memory device of claim 1, wherein the channel layer (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62) and the source structure (244) are made of different materials (228 is amorphous silicon and 244 is monocrystalline silicon).
Re claim 5: Lu teaches the semiconductor memory device of claim 1, wherein the vertical structure (VS) further comprises conductive pads (bit line contacts 226; e.g. paragraph 68; hereinafter “CP”) that are respectively in lower portions of the vertical channel holes (VCH) and gap-fill insulating patterns (dielectric layer 229; e.g. paragraph 60) in the vertical channel holes, wherein lower portions of the first portions (1P) respectively extend along top surfaces of the conductive pads (CP), and wherein the gap-fill insulating patterns (229) are spaced apart from the conductive pads (CP) with the lower portions of the first portions (1P) therebetween .
Re claim 6: Lu teaches the semiconductor memory device of claim 1, wherein each of the first portions (1P) has a closed end pipe shape (1P has a closed end pipe shape much like as shown in fig. 6A of the instant application) in a cross-sectional view.
Re claim 8: Lu teaches the semiconductor memory device of claim 1, wherein a top surface of the second portion (2P) is in contact (electrical contact) with the bottom surface of the source structure (244).
Re claim 9: Lu teaches the semiconductor memory device of claim 1, wherein the vertical structure (VS) further comprises data storage patterns (dielectric layer 229; e.g. paragraph 60) that are respectively in the vertical channel holes (VCH), and wherein a bottom surface of the second portion (2P) is on top surfaces of the data storage patterns (229).
Re claim 11: Lu teaches the semiconductor memory device of claim 1, wherein a thickness of the second portion (2P) in a direction perpendicular to the substrate is less than that of the source structure (244).
Re claim 13: Lu teaches (e.g. figs. 2 and labeled fig. 2 above) a three-dimensional semiconductor memory device, comprising: a substrate (202); a peripheral circuit structure (peripheral interconnect layer 222; e.g. paragraph 57) on the substrate (202); and a cell array structure (262) on the peripheral circuit structure (222), the cell array structure (262) comprising: a cell array region (region of 262 labeled “CAR”); a cell array contact region (region of 262 labeled “CACR”) extended from the cell array region (CAR) in a direction parallel to a top surface of the substrate (202); a stack (alternating conductor/dielectric stack 242; e.g. paragraph 59) that includes interlayer insulating layers (dielectric layer 236; e.g. paragraph 59) and conductive patterns (conductor layer 234; e.g. paragraph 59) alternately stacked with one another; a source structure (244; e.g. paragraph 62) on the stack (242); a vertical structure (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62; hereinafter “VS”) that extends in the stack (242) and is electrically connected to a bottom surface of the source structure (244); cell contact plugs (word line contacts 257 and bit line contacts 226; e.g. paragraph 68; hereinafter “CP”) in the cell array contact region (region of 223) and electrically connected (257 contacts 234) to the conductive patterns (234), respectively; a source contact plug (contact for 232 within 223) in the cell array contact region (region of 223) and electrically connected to the bottom surface of the source structure (244); and bit lines (bit lines within metallization layer 223 connected to bit line contacts 226; e.g. paragraph 68) electrically connected to the cell contact plugs (226), wherein the vertical structure (VS) comprises a channel layer (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62) that includes first portions (channel 228, epi layer 251; hereinafter “1P”) respectively in vertical channel holes (holes for VS; hereinafter “VCH”) extending in the stack (242), and a second portion (doped region 250; hereinafter “2P”) that extends in a region between the stack (242) and the source structure (244), wherein the second portion (2P) extends between adjacent vertical channels holes (VCH) of the stack (242), wherein the second portion (2P) is in contact with the first portions (1P) within the adjacent vertical channel holes (VCH), wherein the second portion (2P) is in both the cell array region (CAR) and the cell array contact region (CACR), and the second portion (2P) extends between the cell contact plugs (258) and the source structure (244).
Re claim 14: Lu teaches the semiconductor memory device of claim 13, wherein the channel layer (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62) and the source structure (244) are made of different materials (228 is amorphous silicon and 244 is monocrystalline silicon).
Re claim 18: Lu teaches the semiconductor memory device of claim 13, wherein a thickness of the second portion (2P) in a direction perpendicular to the substrate is less than that of the source structure (244).
Re claim 19: Lu teaches the semiconductor memory device of claim 13, wherein the vertical structure (VS) further comprises data storage patterns (dielectric layer 229; e.g. paragraph 60) that are respectively in the vertical channel holes (VCH), and wherein a bottom surface of the second portion (2P) is on top surfaces of the data storage patterns (229).
Re claim 20: Lu teaches the semiconductor memory device of claim 13, wherein each of the first portions (1P) has a closed end pipe shape (1P has a closed end pipe shape much like as shown in fig. 6A of the instant application) in a cross-sectional view.
Re claim 17: Lu teaches (e.g. figs. 2 and labeled fig. 2 above) an electronic system, comprising: a three-dimensional semiconductor memory device (3D NAND structure 100; e.g. paragraph 52) that includes a substrate (202), a peripheral circuit structure (peripheral interconnect layer 222; e.g. paragraph 57) on the substrate (202), and a cell array structure (262) on the peripheral circuit structure (222), the cell array structure (262) comprising : a cell array region (region of 262 labeled “CAR”) and a cell array contact region (region of 262 labeled “CACR”); and a controller (memory array and peripheral devices controlling signals to/from the array; e.g. paragraph 4) electrically connected to the three-dimensional semiconductor memory device (100) through an input/output pad (224; e.g. paragraph 68) and configured to control the three-dimensional semiconductor memory device (100), wherein the cell array structure (262) further comprises: a stack (alternating conductor/dielectric stack 242; e.g. paragraph 59) that includes interlayer insulating layers (dielectric layer 236; e.g. paragraph 59) and conductive patterns (conductor layer 234; e.g. paragraph 59) alternately stacked with one another; a source structure (244; e.g. paragraph 62) on the stack (242); and a vertical structure (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62; hereinafter “VS”) that extends in the stack (242) and is electrically connected to a bottom surface of the source structure (244), cell contact plugs (word line contacts 258; e.g. paragraph 64) in the cell array contact region (CACR) and connected to the conductive patterns (234), respectively and wherein the vertical structure (VS) comprises a channel layer (channel 228, epi layer 251, doped region 250; e.g. paragraphs 60, 62) that includes first portions (channel 228, epi layer 251; hereinafter “1P”) respectively in vertical channel holes (holes for VS; hereinafter “VCH”) extending in the stack (242), and a second portion (doped region 250; hereinafter “2P”) that extends in a region between the stack (242) and the source structure (244) and is electrically connected to the first portions (1P), wherein the second portion (2P) extends between adjacent vertical channels holes (VCH) of the stack (242), wherein the second portion (2P) is in both the cell array region (CAR) and the cell array contact region (CACR), and the second portion (2P) extends between the cell contact plugs (258) and the source structure (244).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 7, 10, 12, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claims 1 and 13 above, and further in view of Matsuda et al. (US PGPub 2022/0076965; hereinafter “Matsuda”).
Re claims 4 and 15: Lu teaches substantially the entire device as claimed in claim 1 and 13, respectively, except explicitly teaching the semiconductor memory device wherein the vertical structure further comprises gap-fill insulating patterns in the vertical channel holes, respectively, and wherein top surfaces of the gap-fill insulating patterns are in contact with the bottom surface of the source structure.
Matsuda teaches (e.g. fig. 2) the vertical structure further comprises gap-fill insulating patterns (insulating core layer 50; e.g. paragraph 49) in the vertical channel holes (opening OP2), respectively, and wherein top surfaces of the gap-fill insulating patterns (50) are in contact (upper surface of 50 is in electrical contact with the source structure) with the bottom surface of the source structure (43 of Lu).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the dielectric core in the channel as taught by Matsuda in the device of Lu since Lu is silent as to the material of the commonly known structure of the dielectric core and would ensure proper confinement of the electrons in the channel layer.
Re claims 7 and 16: Lu teaches substantially the entire device as claimed in claim 1 and 13, respectively, except explicitly teaching the semiconductor memory device wherein the vertical structure further comprises: gap-fill insulating patterns in the vertical channel holes, respectively; and conductive pads in lower portions of the vertical channel holes, respectively, and wherein the first portions extend in regions between the gap-fill insulating patterns and the conductive pads, respectively.
Matsuda teaches (e.g. fig. 2) the vertical structure further comprises: gap-fill insulating patterns (insulating core layer 50; e.g. paragraph 49) in the vertical channel holes (opening OP2), respectively; and conductive pads (CP of Lu) in lower portions of the vertical channel holes (VCH of Lu), respectively, and wherein the first portions (1P of Lu) extend in regions between the gap-fill insulating patterns (50) and the conductive pads (CP of Lu), respectively.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the dielectric core in the channel as taught by Matsuda in the device of Lu since Lu is silent as to the material of the commonly known structure of the dielectric core and would ensure proper confinement of the electrons in the channel layer.
Re claim 10: Lu teaches substantially the entire device as claimed in claim 1 except explicitly teaching the semiconductor memory device, wherein the vertical structure further comprises gap-fill insulating patterns in the vertical channel holes, respectively, and wherein top surfaces of the gap-fill insulating patterns are at substantially a same level as a top surface of the second portion in a direction perpendicular to the substrate, relative to the substrate.
Matsuda teaches (e.g. fig. 2) the vertical structure further comprises gap-fill insulating patterns (insulating core layer 50; e.g. paragraph 49) in the vertical channel holes (opening OP2), respectively, and wherein top surfaces of the gap-fill insulating patterns (50) are at substantially a same level as a top surface of the second portion (2P of Lu/upper portion of OP2 of Matsuda) in a direction perpendicular to the substrate, relative to the substrate (10).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the dielectric core in the channel as taught by Matsuda in the device of Lu since Lu is silent as to the material of the commonly known structure of the dielectric core and would ensure proper confinement of the electrons in the channel layer.
Re claim 12: Lu teaches substantially the entire device as claimed in claim 1 except explicitly teaching the semiconductor memory device, wherein the vertical structure further comprises gap-fill insulating patterns in the vertical channel holes, respectively, and wherein top surfaces of the gap-fill insulating patterns are at a level higher than a top surface of the stack in a direction perpendicular to the substrate, relative to the substrate.
Matsuda teaches (e.g. fig. 2) the vertical structure further comprises gap-fill insulating patterns (insulating core layer 50; e.g. paragraph 49) in the vertical channel holes (opening OP2), respectively, and wherein top surfaces of the gap-fill insulating patterns (50) are at a level higher than a top surface of the stack (40, 70) in a direction perpendicular to the substrate, relative to the substrate (10).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the dielectric core in the channel as taught by Matsuda in the device of Lu since Lu is silent as to the material of the commonly known structure of the dielectric core and would ensure proper confinement of the electrons in the channel layer.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 2 above, and further in view of Kim et al. (US PGPub 2020/0194448; hereinafter “Kim”).
Re claim 3: Lu teaches substantially the entire structure as recited in claim 2 except explicitly teaching the semiconductor memory device, wherein the channel layer comprises at least one of SiGe, Ge, ZTO, IGZO, InAs, or InGaAs.
Kim teaches the channel layer (vertical channel VS; e.g. paragraph 52) comprises at least one of SiGe, Ge, ZTO, IGZO, InAs, or InGaAs (material of vertical channel VS is Si or Ge; e.g. paragraph 52).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the Ge for the channel of the memory device as taught by Kim in the device of Lu in order to have the predictable result of using a known equivalent group IV semiconductor which has superior carrier mobility characteristics and would improve device performance.
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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