Prosecution Insights
Last updated: April 19, 2026
Application No. 18/317,521

SEMICONDUCTOR PACKAGE

Non-Final OA §102§103
Filed
May 15, 2023
Examiner
GREEN, TELLY D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
85%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1044 granted / 1280 resolved
+13.6% vs TC avg
Minimal +4% lift
Without
With
+3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
48 currently pending
Career history
1328
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.2%
+14.2% vs TC avg
§102
25.3%
-14.7% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1280 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species 1, Embodiment I, Figs. 1, 2, item 10, claims 1-20, in the reply filed on January 21, 2026 is acknowledged. The traversal is on the ground(s) that “the search and examination of all the claims may be made without serious burden”. This is not found persuasive because this would require the Examiner to search for multiple species/embodiments/inventions. The MPEP states that there can be only one patent per invention, hence one invention per application. This also insures any future amendments during prosecution read on the Applicant’s elected species/embodiment/invention. The requirement is still deemed proper and is therefore made FINAL. Action on the merits is as follows: Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an internal wiring and an internal via in the interlayer insulating layer” must be shown or the feature(s) canceled from the claim(s). Examiner notes that substrate (item 11) and the first interlayer insulating layer (item 21) has a TSV (item 50) going through it (See figure 1). There is only one internal via (not labeled) in the first interlayer insulating layer (item 21). Internal wirings (item 31) and internal via (item 32) exist only in the second interlayer insulating layer (item 22). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 U.S.C. 102 or 103(a) In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Lee et al. (Lee) (US 2016/0155686 A1 now US 9,806,004 B2). In regards to claim 1, Lee (Figs. 1A-2H and associated text and items) discloses a semiconductor package (Figs. 1A-1H) comprising: a substrate (item 11) including a first surface (top surface of item 11) and a second surface (bottom surface of item 11) opposite to the first surface (top surface of item 11); a connecting circuit (item 40) on the first surface (top surface of item 11) of the substrate (item 11); a through silicon via (TSV) structure (item 50) penetrating the substrate (item 11); a first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63) on the connecting circuit (item 40); a second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74) on the second surface (bottom surface of item 11) of the substrate (item 11); a first bumping pad (items 80, 85) inside the first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63); and a second bumping pad (item 90) inside the second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74), wherein the first bumping pad (items 80, 85) comprises, a first pad plug (items 83, 88), and a first seed layer (items 81, 82, 86, or 87) surrounding a lower surface and sidewalls of the first pad plug (items 83, 88), wherein the second bumping pad (item 90) comprises, a second pad plug (item 93), and a second seed layer (item 91 or 92) surrounding an upper surface and sidewalls of the second pad plug (item 90), and wherein the first seed layer (items 81, 82, 86, or 87) and the second seed layer (item 91 or 92) comprise materials having different reactivities to water (paragraphs 53, 58, 62, titanium (Ti), copper (Cu), nickel (Ni), tungsten (W), or metal alloys thereof such as titanium-nickel (TiNi) or titanium-tungsten (TiW)). Examiner notes, while Lee does not specifically/explicitly disclose that the first seed layer and the second seed layer comprise materials having different reactivities to water, Lee does disclose the same list of potential materials as the Applicant and would share the same characteristics. It would have been obvious to modify the invention to include a first seed layer and a second seed layer that comprise materials having different reactivities to water, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416). In regards to claim 2, Lee (Figs. 1A-2H and associated text and items) discloses wherein reactivity to water of the second seed layer (item 91 or 92) is less than reactivity to water of the first seed layer (items 81, 82, 86, or 87). In regards to claim 3, Lee (Figs. 1A-2H and associated text and items) discloses wherein an upper surface of the first bumping pad (items 80, 85) is coplanar with an upper surface of the first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63), and a lower surface of the second bumping pad (item 90) is coplanar with a lower surface of the second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74). In regards to claim 4, Lee (Figs. 1A-2H and associated text and items) discloses wherein the first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63, paragraph 56) comprises a different material from the second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74, paragraphs 63, 64, 97, 98). In regards to claim 5, Lee (Figs. 1A-2H and associated text and items) discloses wherein a density of the first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63, paragraph 56) is greater than a density of the second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74, paragraphs 63, 64, 97, 98). Examiner notes that Lee discloses the same list of potential materials as the Applicant and would share the same characteristics. In regards to claim 6, Lee (Figs. 1A-2H and associated text and items) discloses wherein the first bumping pad (items 80, 85) further comprises a first barrier layer (items 81, 86) surrounding a lower surface and outer walls of the first seed layer (items 82, 87), and the first barrier layer (items 81, 86) contacts the connecting circuit (item 40). Examiner notes that the Applicant has not given a special definition to the term “contact(s)”, therefore certain features can be in “direct” or “indirect” contact with one another. In regards to claim 7, Lee (Figs. 1A-2H and associated text and items) discloses wherein the second bumping pad (item 90) further comprises a second barrier layer (item 91) surrounding an upper surface and outer walls of the second seed layer (item 92), and the second barrier layer (item 91) contacts the TSV structure (item 50). In regards to claim 8, Lee (Figs. 1A-2H and associated text and items) discloses a semiconductor package (Figs. 1A-1H) comprising: a substrate item 11) including a first surface (top surface of item 11) and a second surface (bottom surface of item 11) opposite to the first surface (top surface of item 11); an interlayer insulating layer (items 21 or 21 plus 22) on the first surface (top surface of item 11) of the substrate (item 11); a through silicon via (TSV) structure (item 50) penetrating the substrate (item 11) and the interlayer insulating layer (item 21); a connecting circuit (item 40) on the interlayer insulating layer (item 21), the connecting circuit (item 40) including a TSV connecting via (items 42, 44) that is electrically connected to the TSV structure (item 50); a first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63) on the connecting circuit (item 40); a second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74) on the second surface of the substrate (item 11); a first bumping pad (items 80, 85) inside the first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63,); and a second bumping pad (item 90) inside the second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74), wherein the first bumping pad (items 80, 85) includes, a first pad plug (items 83, 88), a first seed layer (items 82, 87) surrounding a lower surface and sidewalls of the first pad plug (items 83, 88), and a first barrier layer (items 81, 86) surrounding a lower surface and outer walls of the first seed layer (items 82, 87), wherein the second bumping pad (item 90) includes, a second pad plug (item 93), a second seed layer (item 92) surrounding a lower surface and sidewalls of the second pad plug (item 93), and a second barrier layer (item 91) surrounding a lower surface and outer walls of the second seed layer (item 92), and wherein reactivity to water of the second seed layer (item 92) is less than reactivity to water of the first seed layer (items 82, 87). Examiner notes, while Lee does not specifically/explicitly disclose wherein reactivity to water of the second seed layer is less than reactivity to water of the first seed layer, Lee (paragraphs 53, 58, 62) does disclose the same list of potential materials (titanium (Ti), copper (Cu), nickel (Ni), tungsten (W), or metal alloys thereof such as titanium-nickel (TiNi) or titanium-tungsten (TiW)) as the Applicant and would share the same characteristics. It would have been obvious to modify the invention to include a second seed layer with less reactivity to water than the first seed layer, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416). In regards to claim 9, Lee (Figs. 1A-2H and associated text and items) discloses wherein the first seed layer (items 82, 87) comprises tantalum (Ta) (paragraph 53), and the second seed layer (item 92) comprises titanium (Ti) (paragraph 62). In regards to claim 10, Lee (Figs. 1A-2H and associated text and items) discloses wherein resistance to a temperature of the first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63, paragraph 56) is greater than resistance to a temperature of the second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74, paragraphs 63, 64, 97, 98). Examiner notes that Lee discloses the same potential materials for the first and second passivation layers as the Applicant and would therefore share the same characteristics. In regards to claim 11, Lee (Figs. 1A-2H and associated text and items) discloses wherein the first pad plug (items 83, 88) and the second pad plug (item 93) comprise an identical material (paragraphs 53, 58, 62, copper (Cu) or nickel (Ni)). In regards to claim 12, Lee (Figs. 1A-2H and associated text and items) discloses wherein each of a lower surface of the first bumping pad (items 80, 85) and an upper surface of the second bumping pad (item 90) has a flat shape. Examiner notes that the Applicant has not claimed that the entire upper surface of the second bumping pad has a flat shape. It would have been obvious to modify the invention to include a lower surface of the first bumping pad (items 80, 85) and an upper surface/entire upper surface of the second bumping pad (item 90) having a flat shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). In regards to claim 13, Lee (Figs. 1A-2H and associated text and items) discloses wherein the first barrier layer (items 81, 86, paragraphs 88, 113, titanium nitride (TiN) or tantalum nitride (TaN), titanium nitride (TiN) and tantalum nitride (TaN)) and the second barrier layer (item 91, paragraph 101, , titanium nitride (TiN) or tantalum nitride (TaN)) comprise different materials from each other. It would have been obvious to modify the invention to include a first barrier layer and a second barrier layer comprised of different materials, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416). In regards to claim 14, Lee (Figs. 1A-2H and associated text and items) discloses wherein the first seed layer (items 82, 87) and the first barrier layer (items 81, 86) comprise an identical material (paragraphs 53, 88, 113, titanium Ti), or the second seed layer (item 92) and the second barrier layer(item 91) comprise an identical material (paragraph 101, titanium Ti). In regards to claim 15, Lee (Figs. 1A-2H and associated text and items) discloses a transistor (item 15) on the first surface of the substrate (item 11); and an internal wiring (item 31) and an internal via (item 32) in the interlayer insulating layer (item 21), wherein the internal via (item 32) is electrically connected to the substrate (item 11) or the transistor (item 15). In regards to claim 16, Lee (Figs. 1A-2H and associated text and items) discloses a semiconductor package (Figs. 1A-1H) comprising: a substrate item 11) including a first surface (top surface of item 11) and a second surface (bottom surface of item 11) opposite to the first surface (top surface of item 11); a transistor (item 15) on the first surface of the substrate (item 11); an interlayer insulating layer (items 21 or 21 plus 22) on the first surface (top surface of item 11) of the substrate (item 11), and covering the transistor (item 15); a through silicon via (TSV) structure (item 50) penetrating the substrate (item 11) and the interlayer insulating layer (item 21); a connecting circuit (item 40) on the interlayer insulating layer (item 21), the connecting circuit (item 40) including a TSV connecting via (items 42, 44) that is electrically connected to the TSV structure (item 50); a first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63) on the connecting circuit (item 40); a second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74) on the second surface of the substrate (item 11); a first bumping pad (items 80, 85) inside the first passivation layer (items 61, 62, 63, 61 plus 62, or 61 plus 62 plus 63,); and a second bumping pad (item 90) inside the second passivation layer (items 71, 72, 73, 74, 71 plus 74, 71 plus 73, 72 plus 73 plus 74 or 71 plus 72 plus 73 plus 74), wherein the first bumping pad (items 80, 85) includes, a first pad plug (items 83, 88), a first seed layer (items 82, 87) surrounding a lower surface and sidewalls of the first pad plug (items 83, 88), and a first barrier layer (items 81, 86) surrounding a lower surface and outer walls of the first seed layer (items 82, 87), wherein the second bumping pad (item 90) includes, a second pad plug (item 93), a second seed layer (item 92) surrounding a lower surface and sidewalls of the second pad plug (item 93), and a second barrier layer (item 91) surrounding a lower surface and outer walls of the second seed layer (item 92), and wherein reactivity to water of the second seed layer (item 92) is less than reactivity to water of the first seed layer (items 82, 87). Examiner notes, while Lee does not specifically/explicitly disclose wherein reactivity to water of the second seed layer is less than reactivity to water of the first seed layer, Lee (paragraphs 53, 58, 62) does disclose the same list of potential materials (titanium (Ti), copper (Cu), nickel (Ni), tungsten (W), or metal alloys thereof such as titanium-nickel (TiNi) or titanium-tungsten (TiW)) as the Applicant and would share the same characteristics. It would have been obvious to modify the invention to include a second seed layer with less reactivity to water than the first seed layer, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416). In regards to claim 17, Lee (Figs. 1A-2H and associated text and items) discloses wherein the reactivity to water of the first barrier layer (items 81, 86) is greater than the reactivity to water of the second barrier layer (item 91). Examiner notes the Lee discloses the same list of potential materials for the first and second barrier layers as the Applicant and would therefore share the same characteristics, if one of ordinary skill in the art desired such a structure. In regards to claim 18, Lee (Figs. 1A-2H and associated text and items) discloses wherein the first seed layer (items 82, 87) or the first barrier layer (items 81, 86) comprises tantalum (Ta) (paragraphs 53, 58), and the second seed layer (item 92) or the second barrier layer (item 91) comprises titanium (Ti) (paragraph 62). In regards to claim 19, Lee does not specifically disclose wherein a range of a horizontal width of the first bumping pad or the second bumping pad is 2 micrometers to 10 micrometers, a range of a vertical thickness of the first bumping pad is 0.3 micrometers to 3 micrometers, and a range of a vertical thickness of the second bumping pad is 0.2 micrometers to 2 micrometers. It would have been obvious to modify the invention to include a range of a horizontal width of the first bumping pad or the second bumping pad being 2 micrometers to 10 micrometers, a range of a vertical thickness of the first bumping pad being 0.3 micrometers to 3 micrometers, and a range of a vertical thickness of the second bumping pad being 0.2 micrometers to 2 micrometers, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). )). Examiner notes that the Applicant has not given any criticality to size/shape as to where they yield an advantage or unexpected result. It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a range of a horizontal width of the first bumping pad or the second bumping pad being 2 micrometers to 10 micrometers, a range of a vertical thickness of the first bumping pad being 0.3 micrometers to 3 micrometers, and a range of a vertical thickness of the second bumping pad being 0.2 micrometers to 2 micrometers, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)). Examiner notes that the Applicant has not given any criticality to these values or ranges as to where they yield an advantage or unexpected result. In regards to claim 20, Lee (Figs. 1A-2H and associated text and items) discloses wherein the connecting circuit (item 40) comprises, a lower TSV pad (item 41) contacting the TSV structure (item 50) on the interlayer insulating layer (item 21), a lower TSV connecting via (item 42) on the lower TSV pad (item 41), a TSV connecting wiring (item 43) on the lower TSV connecting via (item 42), an upper TSV connecting via (item 44) on the TSV connecting wiring (item 43) and in contact with the TSV connecting wiring (item 43), and an upper TSV pad (item 45) on the upper TSV connecting via (item 44), and an upper surface of the upper TSV pad (item 45) contacts a lower surface of the first bumping pad (item 80). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TELLY D. GREEN Examiner Art Unit 2898 /TELLY D GREEN/ Primary Examiner, Art Unit 2898 February 4, 2026
Read full office action

Prosecution Timeline

May 15, 2023
Application Filed
Feb 04, 2026
Non-Final Rejection — §102, §103
Mar 10, 2026
Interview Requested
Mar 23, 2026
Examiner Interview Summary
Mar 23, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
85%
With Interview (+3.7%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1280 resolved cases by this examiner. Grant probability derived from career allow rate.

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