DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 9/23/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Ahn et al (US 2020/0075627).
1. (Currently amended) A memory device comprising:
a stack structure (Fig.2M (S1/S2) and [0037]) including a plurality of conductive layers (Fig.2M (400) and [0075]) and a plurality of insulating layers (Fig.2M (120) and [0032]), which are alternately stacked in a first direction (Fig.2M);
a plurality of first plugs (Fig.2M (350- first plug is in S1 stack) and [0063]) disposed in the stack structure (Fig.2M (S1/S2) and [0037]), the plurality of first plugs (Fig.2M (350) and [0063]) extending in the first direction; and
a first support structure (Fig.2M (450) and [0063]) disposed in the stack structure (Fig.2M (S1/S2) and [0037]), the first support structure (Fig.2M (450) and [0063]) being adjacent to at least one of the plurality of first plugs (Fig.2M (350) and [0063]), wherein the first support structure (Fig.2M (450) and [0063]) includes an insulating structure (Fig.2M (155) and [0070]) and a second plug (Fig.2M (255) and [0066]), which are stacked in the first direction, [[and]] wherein each of the plurality of first plugs (Fig.2M (350- first plug is within the S1 stack) and [0063]) and the second plug (Fig.2M (350/255- second plug is within the S2 stack) includes a channel layer (Fig.2M (352) and [0064]);
wherein the insulating structure (Fig.2M (155) and [0070]) has a top surface facing the second plug (Fig.2M (350/255- second plug is within the S2 stack),and wherein the channel layer of the second plug (Fig.2M (352) and [0064]) extends onto the top surface of the insulating structure (Fig.2M (155) and [0070]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2020/0258900) in further view of Ahn et al (US 2020/0075627).
In reference to claim 1, Lee teaches the following claimed limitations:
1. (Original) A memory device comprising:
a stack structure (Fig.1C (CST) and [0041]) including a plurality of conductive layers (Fig.1C (21A/21B) and [0041]) and a plurality of insulating layers (Fig.1C (22A/B) and [0041]), which are alternately stacked in a first direction ( y-direction- See Fig. 1C);
a plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050]) disposed in the stack structure (Fig.1C (CST) and [0041]), the plurality of first plugs extending in the first direction ( y-direction- See Fig. 1C); and
a first support structure (Fig.1C (CH) and [0045-0050]) disposed in the stack structure (Fig.1C (CST) and [0041]), the first support structure (Fig.1C (CH) and [0045-0050]) being adjacent to at least one of the plurality of first plugs (Fig.1C (P1 of SP2; see also Fig.1A (P1 of SP2) and [0029/0032/0036]), wherein the first support structure (Fig.1C (CH) and [0045-0050]) includes an insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]) and a second plug (Fig.1C (PL2) and [0029]), which are stacked in the first direction (y-direction- See Fig. 1C), and wherein each of the plurality of first plugs (Fig.1C (PL1) and [0050]) and the second plug (Fig.1C (PL2) and [0029]) includes a channel layer (Fig.1C (23A/B) and [0050]).
Lee further teaches wherein the gap-fill layer (Fig.1C (14/24) and [0032]) has a top surface facing the second plug (Fig.1C (PL2) and [0029]), and wherein the channel layer (Fig.1C (23B) and [0050]) of the second plug extends onto the top surface of the gap fill layer (Fig.1C (14/24) and [0032]).
Lee fails to teach Applicant’s amended limitation: wherein the insulating structure has a top surface facing the second plug, and wherein the channel layer of the second plug extends onto the top surface of the insulating structure.
However, Ahn teaches a similar plug structure including wherein the insulating structure (Fig.2M (155) and [0070]) has a top surface facing the second plug (Fig.2M (350/255- second plug is within the S2 stack),and wherein the channel layer of the second plug (Fig.2M (352) and [0064]) extends onto the top surface of the insulating structure (Fig.2M (155) and [0070]).
It would have been obvious to one of ordinary skill in the art to modify Lee’s gap fill material to include an insulating material as taught by Ahn because both structures are for support and are not utilized as a channel plug.
2. (Original) The memory device of claim 1, further comprising a plurality of contact plugs (Fig.1C (CP1/2) and [0021]) connected to the plurality of conductive layers (Fig.1C (21A/B) and [0041]), wherein the stack structure (Fig.1C (CST) and [0041]) includes a contact region having the plurality of contact plugs (Fig.1C (CP1/2) and [0021]) and a cell region (Fig.1C (C) and [0041]) having the plurality of first plugs (Fig.1C (PL1) and [0049]), and wherein the first support structure (Fig.1C (CH) and [0045-0050]) is disposed between the contact region (Fig.1C (CP1/2) and [0021]) of the stack structure (Fig.1C (CST) and [0041]).and the cell region (Fig.1C (C) and [0041]) of the stack structure (Fig.1C (CST) and [0041]).
3. (Original) The memory device of claim 1, further comprising a slit isolating the stack structure into a first memory cell array and a second memory cell array, wherein at least one of the plurality of first plugs is adjacent to the first support structure in a direction in which the slit extends (not shown- but described- [0078-0080]).
4. (Original) The memory device of claim 1, comprising a plurality of second support structures (Fig.1C (SP1/SP2) and [0021]) disposed in the stack structure (Fig.1C (CST) and [0041]) at both ends of the stack structure (Fig.1C (CST) and [0041]) with the plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050])interposed therebetween, wherein the first support structure (Fig.1C (CH) and [0045-0050]) is disposed between the plurality of second support structures (Fig.1C (SP1/SP2) and [0021]) and the plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050]).
5. (Original) The memory device of claim 4, wherein the plurality of second support structures (Fig.1C (SP1/SP2) and [0021]) include an insulating material (Fig.1C (SP1/SP2- insulating material 19) and [0035] extending longer in the first direction (y-direction) than the insulating structure of the first support structure (Fig.1C (CH/ 19) and [0035].
6. (Original) The memory device of claim 1, wherein a length of the second plug (Fig.1C (PL2/P2) and [0029]) is shorter than a length of the plurality of first plugs (Fig.1C (SP1) and [0029/0032/0036]) in the first direction (y-direction).
7. (Original) The memory device of claim 1, wherein a length of the insulating structure (Fig.1C (25A/B) and [0050]see also Fig.10D (25A/B) and [0099]) is shorter than a length of the plurality of first plugs (Fig.1C (SP1) and [0029/0032/0036]) in the first direction (y-direction).
8. (Original) The memory device of claim 1, wherein the bottom of the insulating structure (Fig.1C (25A/B) and [0050]see also Fig.10D (25A/B) and [0099])and the bottom of the plurality of first plugs (Fig.1C (SP1) and [0029/0032/0036]) are substantially on the same plane (Fig.1C).
9. (Original) The memory device of claim 1, further comprising a source layer (Fig.2B (30 and [0058]) disposed on the bottom of the stack structure (Fig.2B( ST1) and [0058]), wherein the channel layers of the plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050]) are connected to the source layer (Fig.2B (30 and [0058]), and wherein the channel layer (Fig.1C (23A/B) and [0050]) of the second plug (Fig.1C (PL2) and [0029]) is spaced apart from the source layer (Fig.2B (30 and [0058]) by the insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]).
10. (Original) The memory device of claim 9, wherein the insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]) is connected to the source layer (Fig.2B (30 and [0058]).
11. (Original) The memory device of claim 1, wherein each of the plurality of first plugs and the second plug further includes a tunnel insulating layer, a data storage layer, and a blocking layer, which surround the channel layer [0050].
12. (Original) The memory device of claim 1, wherein each of the plurality of first plugs has a stepped corner portion on a sidewall thereof (Fig.1A (P) and [0031]).
13. (Original) The memory device of claim 12, wherein the corner portion (Fig.1A (P) and [0031]) of each of the plurality of first plugs and an upper surface of the insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]) are substantially on the same plane (Fig.1C).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lee et al (US 20230320086); Choi et al (US 20240324203) and Kang et al (US 20210091109) teach similar structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
06/12/26
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