DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 9/23/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lee (US 2020/0258900).
1. (Original) A memory device comprising:
a stack structure (Fig.1C (CST) and [0041]) including a plurality of conductive layers (Fig.1C (21A/21B) and [0041]) and a plurality of insulating layers (Fig.1C (22A/B) and [0041]), which are alternately stacked in a first direction ( y-direction- See Fig. 1C);
a plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050]) disposed in the stack structure (Fig.1C (CST) and [0041]), the plurality of first plugs extending in the first direction ( y-direction- See Fig. 1C); and
a first support structure (Fig.1C (CH) and [0045-0050]) disposed in the stack structure (Fig.1C (CST) and [0041]), the first support structure (Fig.1C (CH) and [0045-0050]) being adjacent to at least one of the plurality of first plugs (Fig.1C (P1 of SP2; see also Fig.1A (P1 of SP2) and [0029/0032/0036]), wherein the first support structure (Fig.1C (CH) and [0045-0050]) includes an insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]) and a second plug (Fig.1C (PL2) and [0029]), which are stacked in the first direction (y-direction- See Fig. 1C), and wherein each of the plurality of first plugs (Fig.1C (PL1) and [0050]) and the second plug (Fig.1C (PL2) and [0029]) includes a channel layer (Fig.1C (23A/B) and [0050]).
2. (Original) The memory device of claim 1, further comprising a plurality of contact plugs (Fig.1C (CP1/2) and [0021]) connected to the plurality of conductive layers (Fig.1C (21A/B) and [0041]), wherein the stack structure (Fig.1C (CST) and [0041]) includes a contact region having the plurality of contact plugs (Fig.1C (CP1/2) and [0021]) and a cell region (Fig.1C (C) and [0041]) having the plurality of first plugs (Fig.1C (PL1) and [0049]), and wherein the first support structure (Fig.1C (CH) and [0045-0050]) is disposed between the contact region (Fig.1C (CP1/2) and [0021]) of the stack structure (Fig.1C (CST) and [0041]).and the cell region (Fig.1C (C) and [0041]) of the stack structure (Fig.1C (CST) and [0041]).
3. (Original) The memory device of claim 1, further comprising a slit isolating the stack structure into a first memory cell array and a second memory cell array, wherein at least one of the plurality of first plugs is adjacent to the first support structure in a direction in which the slit extends (not shown- but described- [0078-0080]).
4. (Original) The memory device of claim 1, comprising a plurality of second support structures (Fig.1C (SP1/SP2) and [0021]) disposed in the stack structure (Fig.1C (CST) and [0041]) at both ends of the stack structure (Fig.1C (CST) and [0041]) with the plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050])interposed therebetween, wherein the first support structure (Fig.1C (CH) and [0045-0050]) is disposed between the plurality of second support structures (Fig.1C (SP1/SP2) and [0021]) and the plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050]).
5. (Original) The memory device of claim 4, wherein the plurality of second support structures (Fig.1C (SP1/SP2) and [0021]) include an insulating material (Fig.1C (SP1/SP2- insulating material 19) and [0035] extending longer in the first direction (y-direction) than the insulating structure of the first support structure (Fig.1C (CH/ 19) and [0035].
6. (Original) The memory device of claim 1, wherein a length of the second plug (Fig.1C (PL2/P2) and [0029]) is shorter than a length of the plurality of first plugs (Fig.1C (SP1) and [0029/0032/0036]) in the first direction (y-direction).
7. (Original) The memory device of claim 1, wherein a length of the insulating structure (Fig.1C (25A/B) and [0050]see also Fig.10D (25A/B) and [0099]) is shorter than a length of the plurality of first plugs (Fig.1C (SP1) and [0029/0032/0036]) in the first direction (y-direction).
8. (Original) The memory device of claim 1, wherein the bottom of the insulating structure (Fig.1C (25A/B) and [0050]see also Fig.10D (25A/B) and [0099])and the bottom of the plurality of first plugs (Fig.1C (SP1) and [0029/0032/0036]) are substantially on the same plane (Fig.1C).
9. (Original) The memory device of claim 1, further comprising a source layer (Fig.2B (30 and [0058]) disposed on the bottom of the stack structure (Fig.2B( ST1) and [0058]), wherein the channel layers of the plurality of first plugs (Fig.1C (P1 and PL1; see also Fig.1A (P1 of SP2)) and [0029/0032/0036/0050]) are connected to the source layer (Fig.2B (30 and [0058]), and wherein the channel layer (Fig.1C (23A/B) and [0050]) of the second plug (Fig.1C (PL2) and [0029]) is spaced apart from the source layer (Fig.2B (30 and [0058]) by the insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]).
10. (Original) The memory device of claim 9, wherein the insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]) is connected to the source layer (Fig.2B (30 and [0058]).
11. (Original) The memory device of claim 1, wherein each of the plurality of first plugs and the second plug further includes a tunnel insulating layer, a data storage layer, and a blocking layer, which surround the channel layer [0050].
12. (Original) The memory device of claim 1, wherein each of the plurality of first plugs has a stepped corner portion on a sidewall thereof (Fig.1A (P) and [0031]).
13. (Original) The memory device of claim 12, wherein the corner portion (Fig.1A (P) and [0031]) of each of the plurality of first plugs and an upper surface of the insulating structure (Fig.1C (25A/B) and [0050] see also Fig.10D (25A/B) and [0099]) are substantially on the same plane (Fig.1C).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lee et al (US 20230320086); Choi et al (US 20240324203) and Kang et al (US 20210091109) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAURA M MENZ/Primary Examiner, Art Unit 2813
12/18/25