DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-21 have been considered but are moot because the new ground of rejection relies on new references for teaching matters specifically challenged in the argument.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9, 12, 13 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-15 of copending Application No. 19/200,201 (Mikami) in view of U.S. Patent Application Publication No. 2005/0230824 (Watanabe) and U.S. Patent Application Publication No. 2021/0202368 (Lin).
Mikami discloses (claims 1, 4, 8)
1. (Currently amended) A semiconductor device comprising:
a substrate;
a device region provided in the substrate;
a terminal covering the device region in a plan view; and
a plurality of pseudo-bumps arranged at a first pitch on the terminal in a state of being opened from a wire.
Mikami fails to disclose
a dense arrangement of the plurality of pseudo-bumps;
at least one genuine bump sparsely arranged on the terminal in a state of being connected to the wire;
wherein each of the at least one genuine bump is spaced apart from one of the plurality of pseudo-bumps closest thereto by a distance that is larger than the first pitch.
Watanabe teaches
A semiconductor device comprising:
a plurality of bumps 13 densely arranged at a first pitch on a terminal 18; and
at least one bump 14 arranged more sparsely than the plurality of bumps 13.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide two different types of bumps densely and sparsely arranged in Mikami. The motivation would be that if the break-down of pseudo-bumps occurs, it does not cause any electrical malfunction because the dummy bump does not configure an electric connection as taught by Watanabe ([0033]). This will reduce the amount of thermal expansion between a board and the semiconductor device by an amount corresponding to the distance between genuine bumps. The reduction may reduce strain and thermal stress.
Lin teaches
A semiconductor device comprising:
wherein each bump 144 is spaced apart from bumps 142 closest thereto by a distance P2 that is larger than the first pitch P1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to consider bump pitch in the modified device of Mikami. The motivation would be the fine pitch bumps may serve as one contact point, and the coarse pitch bumps may serve as a different contact point, and thus the substrate can be used to achieve different electrical connection requirements as taught by Lin ([0023], [0030]).
Okuda discloses
2. The semiconductor device of Claim 1, wherein the plurality of pseudo-bumps 4 are arranged on the terminal with a first occupation area per unit plane area, and wherein the at least one genuine bump 311 is arranged on the terminal with a second occupation area less than the first occupation area per unit area.
Okuda discloses
3. The semiconductor device of Claim 1, wherein the at least one genuine bump 311 includes a plurality of genuine bumps, and wherein the plurality of genuine bumps are sparsely arranged on the terminal 10.
Lin teaches
4. (Currently amended) The semiconductor device of Claim 3, wherein the plurality of genuine bumps 144 are arranged at a second pitch P2 on the terminal (unlabeled), the second pitch larger than the first pitch P1.
Regarding claims 5-9, shifting the position of the bumps would modify the operation of the device. See MPEP 2144.04.
Okuda discloses
5. The semiconductor device of Claim 1, wherein at least three pseudo-bumps of the plurality of pseudo-bumps 4 are densely arranged on the terminal 10.
Okuda discloses
6. The semiconductor device of Claim 5, wherein the at least three pseudo-bumps 4 are arranged in a layout in which the at least three pseudo-bumps are located at vertices of an isosceles triangle in the plan view.
Okuda discloses
7. The semiconductor device of Claim 1, wherein at least seven pseudo-bumps of the plurality of pseudo-bumps 4 are densely arranged on the terminal 10.
Okuda discloses
8. The semiconductor device of Claim 7, wherein six pseudo-bumps of the at least seven pseudo-bumps 4 are arranged around one pseudo-bump of the at least seven pseudo-bumps.
Okuda discloses
9. The semiconductor device of Claim 8, wherein the six pseudo-bumps 4 are arranged in a layout in which the six pseudo-bumps are located at vertices of a hexagon in the plan view, and wherein the one pseudo-bump is arranged in a layout in which the one pseudo-bump is located at a center of the hexagon in the plan view.
Okuda discloses
12. The semiconductor device of Claim 1, wherein each of the plurality of pseudo-bumps includes:
a wide body portion 311 connected to the terminal 10; and
a neck portion 31 which is narrower than the body portion 311 and protrudes from the body portion 311 toward an opposite side of the terminal 10.
Regarding claim 13, removing a portion of the bump would have been obvious if this feature was not desired in Okuda. See MPEP 2144.04.
13. The semiconductor device of Claim 12, wherein each of the plurality of pseudo-bumps includes at least one gouged portion recessed toward a central portion of the neck portion in the neck portion.
Claims 18-20 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-15 of copending Application No. 19/200,201 (Mikami) in view of U.S. Patent Application Publication No. 2005/0230824 (Watanabe) and U.S. Patent Application Publication No. 2021/0202368 (Lin).
Mikami discloses (claims 1, 4, 8)
18. (Currently amended) A semiconductor device comprising:
a substrate;
a device region provided in the substrate;
a terminal covering the device region in a plan view;
a plurality of pseudo-bumps arranged at a first pitch on the terminal in a state of being opened from a wire.
Mikami fails to disclose
a genuine bump that is arranged on the terminal in a state of being connected to the wire and a size smaller than a size of each of the plurality of pseudo-bumps,
wherein the genuine bump is spaced apart from one of the plurality of pseudo-bumps closest thereto by a distance that is larger than the first pitch.
Feng teaches (Fig. 2)
A semiconductor device comprising:
pseudo bumps 202 / 208 not connected to a wire and genuine bumps 220 connected to a wire 218; and
the genuine bumps 220 have a size smaller than a size of each of the pseudo bumps 202 / 208.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide genuine bumps larger than pseudo-bumps in Okuda. The motivation would be merely scaling up the size of the bumps is based on routine engineering design considerations as taught by Feng ([0030]-[0033]). See MPEP 2144.04.
Lin teaches
A semiconductor device comprising:
wherein bump 144 is spaced apart from bumps 142 closest thereto by a distance P2 that is larger than the first pitch P1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to consider bump pitch in the modified device of Okuda. The motivation would be the fine pitch bumps may serve as one contact point, and the coarse pitch bumps may serve as a different contact point, and thus the substrate can be used to achieve different electrical connection requirements as taught by Lin ([0023], [0030]).
Regarding claims 19, 20 shifting the position of the bumps would modify the operation of the device. See MPEP 2144.04.
Feng teaches (Fig. 2)
19. (Currently Amended) The semiconductor device of Claim 18, further comprising
at least one small pseudo-bump that 202 / 208 is arranged around at least one of the plurality of pseudo-bumps on the terminal in a state of being opened from the wire and has a size smaller than the size of the at least one pseudo-bump.
Feng teaches (Fig. 2)
20. (Currently Amended) The semiconductor device of Claim 19, wherein the at least one small pseudo-bump includes a plurality of small pseudo-bumps, and wherein the plurality of small pseudo-bumps are arranged around the at least one pseudo-bump 202 / 208.
Claims 10, 11, 15, 16 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-15 of Mikami in view of Watanabe and Lin as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2023/0010383 (Igarashi).
The combination of references fails to teach
10. The semiconductor device of Claim 1, further comprising:
a thin film portion formed at a bonding portion of each of the plurality of pseudo-bumps in the terminal; and
a thick film portion formed in a region outside the bonding portion of each of the plurality of pseudo-bumps in the terminal.
Igarashi teaches (Fig. 02, [0041])
A semiconductor device comprising:
a thin film portion (under CB) formed at a bonding portion of each of the plurality of bumps CB in the terminal PD; and
a thick film portion (side of CB) formed in a region outside the bonding portion of each of the plurality of bumps CB in the terminal PD.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide both a thick film and thin film portion in the terminal in the modified device of Mikami. The motivation would be to improve reliability of the connection when performing a push-pull test for connection strength evaluation as taught by Irabashi ([0033], [0034], [0045], [0050], [0052], [0055]).
Igarashi teaches (Fig. 02, [0041])
11. The semiconductor device of Claim 10, further comprising a raised portion in which a portion of the terminal PD is thicker than the thick film portion at a bonding edge of each of the plurality of pseudo-bumps in the terminal.
Igarashi teaches (Fig. 02)
15. The semiconductor device of Claim 1, further comprising
a plurality of trench structures DT1 formed in the device region in the substrate SB, wherein each of the plurality of pseudo-bumps overlaps the plurality of trench structures DT1 in the plan view.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a trench structure in the modified device of Mikami. The motivation would be to prevent silicon peeling, oxide film peeling, or the occurrence of cracking more reliably as taught by Irabashi ([0046]).
Igarashi teaches (Fig. 02)
16. The semiconductor device of Claim 15, wherein each of the plurality of pseudo-bumps has a thickness larger than a depth of each of the plurality of trench structures DT1.
Claims 14 is/are is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-15 of Mikami in view of Watanabe and Lin as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2013/0180757 (Uno).
The combination of references fails to teach
14. The semiconductor device of Claim 1, wherein each of the plurality of pseudo-bumps includes:
a bump body containing first metal; and
a metal film containing second metal different from the first metal and covering at least a portion of an outer surface of the bump body.
Uno teaches
A semiconductor device comprising:
a plurality of bumps 3 includes:
a bump body (lower portion) containing first metal (Cu, [0055]); and
a metal film 10 containing second metal (Pd, Au, Ag, or Pt, [0056]) different from the first metal (Cu, [0055]) and covering at least a portion of an outer surface of the bump body (lower portion).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a metal film in the modified device of Mikami. The motivation would be to provide a super-low loop bondability and a ball bondability to be improved as taught by Uno ([0055]).
Claims 17 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-15 of Mikami in view of Watanabe and Lin as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2016/0005827 (Nakano).
The combination of references fails to teach
17. The semiconductor device of Claim 1, further comprising
a control region provided in the substrate, wherein the terminal covers the device region to expose the control region in the plan view.
Nakano teaches
A semiconductor device comprising:
a control region 3 provided in the substrate (not shown, [0079]), wherein the terminal 4 covers the device region 2 to expose the control region 3 in the plan view.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a control region in the modified device of Mikami. The motivation would be they are well-known in the semiconductor device art as taught by Nakano ([0086], [0112]). See MPEP 2144.03.
Claims 21 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-15 of copending Application No. 19/200,201 (Mikami) in view of U.S. Patent Application Publication No. 2005/0230824 (Watanabe).
Mikami discloses (claims 1, 4, 8)
21. (New) A semiconductor device comprising:
a substrate;
a device region provided in the substrate;
a terminal covering the device region in a plan view;
a plurality of pseudo-bumps densely arranged on a portion of the terminal, which covers a high-temperature region of the device region, in a state of being opened from a wire.
Mikami fails to disclose
at least one genuine bump arranged more sparsely than the plurality of pseudo-bumps on the terminal in a state of being connected to the wire.
Watanabe teaches
A semiconductor device comprising:
a plurality of bumps 13 densely arranged at a first pitch on a terminal 18; and
at least one bump 14 arranged more sparsely than the plurality of bumps 13.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide two different types of bumps densely and sparsely arranged in Mikami. The motivation would be that if the break-down of pseudo-bumps occurs, it does not cause any electrical malfunction because the dummy bump does not configure an electric connection as taught by Watanabe ([0033]). This will reduce the amount of thermal expansion between a board and the semiconductor device by an amount corresponding to the distance between genuine bumps. The reduction may reduce strain and thermal stress.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 12, 13 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Patent Application Publication No. 2017/0179108 (Okuda, U.S. counterpart of JP Publication No. 2017147433, cited by Applicant) in view of U.S. Patent Application Publication No. 2005/0230824 (Watanabe) and U.S. Patent Application Publication No. 2021/0202368 (Lin).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Okuda discloses (at least Figs. 6, 14, 15A, 19A)
1. (Currently Amended) A semiconductor device comprising:
a substrate 2;
a device region 55 provided in the substrate 2;
a terminal 10 covering the device region 55 in a plan view;
a plurality of pseudo-bumps 4 arranged at a first pitch on the terminal 10 in a state of being opened from a wire; and
at least one genuine bump 311 arranged on the terminal 10 in a state of being connected to a wire 31.
Okuda fails to disclose
a dense arrangement of the plurality of pseudo-bumps; and
a sparse arrangement of the at least one genuine bumps,
wherein each of the at least one genuine bump is spaced apart from one of the plurality of pseudo-bumps closest thereto by a distance that is larger than the first pitch.
Watanabe teaches
A semiconductor device comprising:
a plurality of bumps 13 densely arranged at a first pitch on a terminal 18; and
at least one bump 14 arranged more sparsely than the plurality of bumps 13.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide two different types of bumps densely and sparsely arranged in Okuda. The motivation would be that if the break-down of pseudo-bumps occurs, it does not cause any electrical malfunction because the dummy bump does not configure an electric connection as taught by Watanabe ([0033]). This will reduce the amount of thermal expansion between a board and the semiconductor device by an amount corresponding to the distance between genuine bumps. The reduction may reduce strain and thermal stress.
Lin teaches
A semiconductor device comprising:
wherein each bump 144 is spaced apart from bumps 142 closest thereto by a distance P2 that is larger than the first pitch P1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to consider bump pitch in the modified device of Okuda. The motivation would be the fine pitch bumps may serve as one contact point, and the coarse pitch bumps may serve as a different contact point, and thus the substrate can be used to achieve different electrical connection requirements as taught by Lin ([0023], [0030]).
Okuda discloses
2. The semiconductor device of Claim 1, wherein the plurality of pseudo-bumps 4 are arranged on the terminal with a first occupation area per unit plane area, and wherein the at least one genuine bump 311 is arranged on the terminal with a second occupation area less than the first occupation area per unit area.
Okuda discloses
3. The semiconductor device of Claim 1, wherein the at least one genuine bump 311 includes a plurality of genuine bumps, and wherein the plurality of genuine bumps are sparsely arranged on the terminal 10.
Lin teaches
4. (Currently amended) The semiconductor device of Claim 3, wherein the plurality of genuine bumps 144 are arranged at a second pitch P2 on the terminal (unlabeled), the second pitch larger than the first pitch P1.
Regarding claims 5-9, shifting the position of the bumps would modify the operation of the device. See MPEP 2144.04.
Okuda discloses
5. The semiconductor device of Claim 1, wherein at least three pseudo-bumps of the plurality of pseudo-bumps 4 are densely arranged on the terminal 10.
Okuda discloses
6. The semiconductor device of Claim 5, wherein the at least three pseudo-bumps 4 are arranged in a layout in which the at least three pseudo-bumps are located at vertices of an isosceles triangle in the plan view.
Okuda discloses
7. The semiconductor device of Claim 1, wherein at least seven pseudo-bumps of the plurality of pseudo-bumps 4 are densely arranged on the terminal 10.
Okuda discloses
8. The semiconductor device of Claim 7, wherein six pseudo-bumps of the at least seven pseudo-bumps 4 are arranged around one pseudo-bump of the at least seven pseudo-bumps.
Okuda discloses
9. The semiconductor device of Claim 8, wherein the six pseudo-bumps 4 are arranged in a layout in which the six pseudo-bumps are located at vertices of a hexagon in the plan view, and wherein the one pseudo-bump is arranged in a layout in which the one pseudo-bump is located at a center of the hexagon in the plan view.
Okuda discloses
12. The semiconductor device of Claim 1, wherein each of the plurality of pseudo-bumps includes:
a wide body portion 311 connected to the terminal 10; and
a neck portion 31 which is narrower than the body portion 311 and protrudes from the body portion 311 toward an opposite side of the terminal 10.
Regarding claim 13, removing a portion of the bump would have been obvious if this feature was not desired in Okuda. See MPEP 2144.04.
13. The semiconductor device of Claim 12, wherein each of the plurality of pseudo-bumps includes at least one gouged portion recessed toward a central portion of the neck portion in the neck portion.
Claims 18-20 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Okuda, cited by Applicant in view of U.S. Patent Application Publication No. 2008/0079173 (Feng) and Lin.
Okuda discloses (at least Figs. 6, 14, 15A, 19A)
18. A semiconductor device comprising:
a substrate 2;
a device region 55 provided in the substrate 2;
a terminal 10 covering the device region 55 in a plan view; and
a plurality of pseudo-bumps 4 arranged at a first pitch on the terminal 10 in a state of being opened from a wire; and
a genuine bump 311 arranged on the terminal 10 in a state of being connected to a wire 31.
Okuda fails to disclose
a genuine bump a size smaller than a size of each of the plurality of pseudo-bumps,
wherein the genuine bump is spaced apart from one of the plurality of pseudo-bumps closest thereto by a distance that is larger than the first pitch.
Feng teaches (Fig. 2)
A semiconductor device comprising:
pseudo bumps 202 / 208 not connected to a wire and genuine bumps 220 connected to a wire 218; and
the genuine bumps 220 have a size smaller than a size of each of the pseudo bumps 202 / 208.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide genuine bumps larger than pseudo-bumps in Okuda. The motivation would be merely scaling up the size of the bumps is based on routine engineering design considerations as taught by Feng ([0030]-[0033]). See MPEP 2144.04.
Lin teaches
A semiconductor device comprising:
wherein bump 144 is spaced apart from bumps 142 closest thereto by a distance P2 that is larger than the first pitch P1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to consider bump pitch in the modified device of Okuda. The motivation would be the fine pitch bumps may serve as one contact point, and the coarse pitch bumps may serve as a different contact point, and thus the substrate can be used to achieve different electrical connection requirements as taught by Lin ([0023], [0030]).
Regarding claims 19, 20 shifting the position of the bumps would modify the operation of the device. See MPEP 2144.04.
Feng teaches (Fig. 2)
19. (Currently Amended) The semiconductor device of Claim 18, further comprising
at least one small pseudo-bump that 202 / 208 is arranged around at least one of the plurality of pseudo-bumps on the terminal in a state of being opened from the wire and has a size smaller than the size of the at least one pseudo-bump.
Feng teaches (Fig. 2)
20. (Currently Amended) The semiconductor device of Claim 19, wherein the at least one small pseudo-bump includes a plurality of small pseudo-bumps, and wherein the plurality of small pseudo-bumps are arranged around the at least one pseudo-bump 202 / 208.
Claims 10, 11, 15, 16 is/are rejected under 35 U.S.C. 103 as being obvious over Okuda in view of Watanabe and Lin as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2023/0010383 (Igarashi).
The combination of references fails to teach
10. The semiconductor device of Claim 1, further comprising:
a thin film portion formed at a bonding portion of each of the plurality of pseudo-bumps in the terminal; and
a thick film portion formed in a region outside the bonding portion of each of the plurality of pseudo-bumps in the terminal.
Igarashi teaches (Fig. 02, [0041])
A semiconductor device comprising:
a thin film portion (under CB) formed at a bonding portion of each of the plurality of bumps CB in the terminal PD; and
a thick film portion (side of CB) formed in a region outside the bonding portion of each of the plurality of bumps CB in the terminal PD.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide both a thick film and thin film portion in the terminal in the modified device of Okuda. The motivation would be to improve reliability of the connection when performing a push-pull test for connection strength evaluation as taught by Irabashi ([0033], [0034], [0045], [0050], [0052], [0055]).
Igarashi teaches (Fig. 02, [0041])
11. The semiconductor device of Claim 10, further comprising a raised portion in which a portion of the terminal PD is thicker than the thick film portion at a bonding edge of each of the plurality of pseudo-bumps in the terminal.
Igarashi teaches (Fig. 02)
15. The semiconductor device of Claim 1, further comprising
a plurality of trench structures DT1 formed in the device region in the substrate SB, wherein each of the plurality of pseudo-bumps overlaps the plurality of trench structures DT1 in the plan view.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a trench structure in the modified device of Okuda. The motivation would be to prevent silicon peeling, oxide film peeling, or the occurrence of cracking more reliably as taught by Irabashi ([0046]).
Igarashi teaches (Fig. 02)
16. The semiconductor device of Claim 15, wherein each of the plurality of pseudo-bumps has a thickness larger than a depth of each of the plurality of trench structures DT1.
Claims 14 is/are rejected under 35 U.S.C. 103 as being obvious over Okuda in view of Watanabe and Lin as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2013/0180757 (Uno).
The combination of references fails to teach
14. The semiconductor device of Claim 1, wherein each of the plurality of pseudo-bumps includes:
a bump body containing first metal; and
a metal film containing second metal different from the first metal and covering at least a portion of an outer surface of the bump body.
Uno teaches
A semiconductor device comprising:
a plurality of bumps 3 includes:
a bump body (lower portion) containing first metal (Cu, [0055]); and
a metal film 10 containing second metal (Pd, Au, Ag, or Pt, [0056]) different from the first metal (Cu, [0055]) and covering at least a portion of an outer surface of the bump body (lower portion).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a metal film in the modified device of Okuda. The motivation would be to provide a super-low loop bondability and a ball bondability to be improved as taught by Uno ([0055]).
Claims 17 is/are rejected under 35 U.S.C. 103 as being obvious over Okuda in view of Watanabe and Lin as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2016/0005827 (Nakano).
The combination of references fails to teach
17. The semiconductor device of Claim 1, further comprising
a control region provided in the substrate, wherein the terminal covers the device region to expose the control region in the plan view.
Nakano teaches
A semiconductor device comprising:
a control region 3 provided in the substrate (not shown, [0079]), wherein the terminal 4 covers the device region 2 to expose the control region 3 in the plan view.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a control region in the modified device of Okuda. The motivation would be they are well-known in the semiconductor device art as taught by Nakano ([0086], [0112]). See MPEP 2144.03.
Okuda discloses (at least Figs. 6, 14, 15A, 19A)
21. (New) A semiconductor device comprising:
a substrate 2;
a device region 55 provided in the substrate 2;
a terminal 10 covering the device region 55 in a plan view;
a plurality of pseudo-bumps 4 arranged on a portion of the terminal 10, which covers a high-temperature region ([0071]) of the device region 55, in a state of being opened from a wire; and
at least one genuine bump 311 arranged on the terminal 10 in a state of being connected to a wire 31.
Okuda fails to disclose
at least one genuine bump arranged more sparsely than the plurality of pseudo-bumps.
Watanabe teaches
A semiconductor device comprising:
a plurality of bumps 13 densely arranged at a first pitch on a terminal 18; and
at least one bump 14 arranged more sparsely than the plurality of bumps 13.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide two different types of bumps densely and sparsely arranged in Okuda. The motivation would be that if the break-down of pseudo-bumps occurs, it does not cause any electrical malfunction because the dummy bump does not configure an electric connection as taught by Watanabe ([0033]). This will reduce the amount of thermal expansion between a board and the semiconductor device by an amount corresponding to the distance between genuine bumps. The reduction may reduce strain and thermal stress.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Nos. RE49332 (Yamamoto), 7,095,107 (Ramakrishnan), 8,525,333 (Kanetaka) teach a semiconductor device having pseudo-bumps.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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