DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I (claims 1-15) and Species A (Fig. 1) in the reply filed on 1.20.2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 1-15 are elected.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1.20.2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5.15.2023 is being considered by the examiner.
Examiner Note
Claims are rejected multiple times over different prior art based on alternative interpretations of the claims and/or of the prior art to show unpatentability of the claims.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20130292741 A1).
Regarding claim 1, Huang discloses an avalanche photodiode (APD) (Fig. 1B), comprising:
a dielectric layer (in 110, [0041] – “the substrate 110 includes…a silicon-on-insulator (SOI) substrate”. The dielectric layer being the “insulator” of the SOI substrate 110);
a silicon layer (the “silicon” of the SOI substrate 110 per [0041]) disposed on (from above) the dielectric layer;
a germanium absorption region (140) disposed on (from above) the silicon layer;
a silicon cap layer (160+170) disposed on (from below) the germanium absorption region, wherein the silicon cap layer comprises a multiplication region (in 160, [0041] – “multiplication layer 160 includes intrinsic Si or lightly doped n-type Si”); and
a cathode electrode (175, [0042] - “n-type metal contacts 175”) coupled to the silicon cap layer.
Note: the term “on” is a broad term per https://www.thefreedictionary.com/on which includes definitions such as “Used to indicate contact with or extent over (a surface) regardless of position” and “Used to indicate proximity”.
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Regarding claim 2, Huang discloses the APD of claim 1, further comprising: a N-doped region (“n++ contact”, Fig. 1B) of the silicon cap layer (160+170), wherein the cathode electrode (175) is connected to the N-doped region (Fig. 1B).
Regarding claim 3, Huang discloses the APD of claim 2, wherein a remaining portion of the silicon cap layer (160+170) is intrinsic silicon or is lighter doped than the N-doped region of the silicon cap layer ([0041] – “the multiplication layer 160 includes intrinsic Si or lightly doped n-type Si. In one embodiment, the contact layer 170 includes n-type Si” vs n++).
Regarding claim 9, Huang discloses an avalanche photodiode (APD) (Fig. 1B annotated above), comprising:
a buried oxide (BOX) layer (the “insulator” of the SOI substrate 110 per [0041]);
a silicon layer (the “silicon” of the SOI substrate 110 per [0041]) disposed on (from above) the BOX layer;
a germanium layer (140) disposed on (from above) the silicon layer;
a silicon cap layer (160+170) disposed on (from below) the germanium layer, wherein the silicon cap layer comprises a multiplication region (in 160); and
a cathode electrode (175) coupled to the silicon cap layer (Fig. 1B).
Note: the term “on” is a broad term per https://www.thefreedictionary.com/on which includes definitions such as “Used to indicate contact with or extent over (a surface) regardless of position” and “Used to indicate proximity”.
Regarding claim 10, Huang discloses the APD of claim 9, further comprising: a N-doped region (“n++ contact”, Fig. 1B) of the silicon cap layer (160+170), wherein the cathode electrode (175) is connected to the N-doped region (Fig. 1B).
Regarding claim 11, Huang discloses the APD of claim 10, wherein a remaining portion of the silicon cap layer (160+170) is intrinsic silicon or is lighter doped than the N-doped region of the silicon cap layer ([0041] – “the multiplication layer 160 includes intrinsic Si or lightly doped n-type Si. In one embodiment, the contact layer 170 includes n-type Si” vs n++).
Claims 7-8 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20130292741 A1).
Regarding claims 7 and 8, Huang fails to disclose (claim 7) the APD of claim 1, wherein a width of the silicon cap layer is at least 500 nm and (claim 8) the APD of claim 7, wherein a thickness of the silicon cap layer is at least 100 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at values within the claimed ranges in Huang so as to optimize device characteristics of the APD such as, for example, enhancing the internal multiplication function and/or adjusting device breakdown voltage by varying the width and thickness of the silicon cap layer.
Regarding claims 14 and 15, Huang fails to disclose (claim 14) the APD of claim 9, wherein a width of the silicon cap layer is at least 500 nm and (claim 15) the APD of claim 14, wherein a thickness of the silicon cap layer is at least 100 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at values within the claimed ranges in Huang so as to optimize device characteristics of the APD such as, for example, enhancing the internal multiplication function and/or adjusting device breakdown voltage by varying the width and thickness of the silicon cap layer.
Claims 1-6 and 9-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masini et al. (US 7397101 B1).
Regarding claim 1, Masini discloses an avalanche photodiode (APD) (Fig. 2), comprising:
a dielectric layer (“Silicon Oxide layer”);
a silicon layer (210) disposed on (from above) the dielectric layer;
a germanium absorption region (235/230/240) disposed on (from above) the silicon layer;
a silicon cap layer (215+220) disposed on (from below) the germanium absorption region, wherein the silicon cap layer comprises a multiplication region (presumed inherent since the claim discloses silicon which is met by the prior art; MPEP 2111 and 2112); and
a cathode electrode (250, N side contact) coupled (via 251) to the silicon cap layer.
Note: the term “on” is a broad term per https://www.thefreedictionary.com/on which includes definitions such as “Used to indicate contact with or extent over (a surface) regardless of position” and “Used to indicate proximity”.
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Regarding claim 2, Masini discloses the APD of claim 1, further comprising: a N-doped region (220) of the silicon cap layer (215+220), wherein the cathode electrode (250) is connected to the N-doped region (220).
Regarding claim 3, Masini discloses the APD of claim 2, wherein a remaining portion (215) of the silicon cap layer (215+220) is intrinsic silicon (215) or is lighter doped than the N-doped region of the silicon cap layer.
Regarding claim 4, Masini discloses the APD of claim 1, wherein the silicon layer (210) is P-doped, further comprising: an anode electrode (245) connected to the silicon layer (Fig. 2).
Regarding claim 5, Masini discloses the APD of claim 1, wherein a portion (230) of the germanium absorption region (235/230/240) contacting the silicon cap layer (215+220) forms a charge layer (inherent since the claimed materials/conductivity are met; MPEP 2111 and 2112), wherein the charge layer is P-doped (Fig. 2).
Regarding claim 6, Masini discloses the APD of claim 5, wherein a remaining portion (235) of the germanium absorption region is undoped germanium (intrinsic) or is lighter doped than the charge layer (Fig. 2).
Regarding claim 9, Masini discloses (Fig. 2 annotated above) an avalanche photodiode (APD), comprising:
a buried oxide (BOX) layer (“Silicon Oxide layer”);
a silicon layer (210) disposed on (from above) the BOX layer;
a germanium layer (235+230+240) disposed on (from above) the silicon layer;
a silicon cap layer (215+220) disposed on (from below) the germanium layer, wherein the silicon cap layer comprises a multiplication region (presumed inherent since the prior art discloses the claimed silicon material; MPEP 2111 and 2112); and
a cathode electrode (250) coupled to the silicon cap layer.
Note: the term “on” is a broad term per https://www.thefreedictionary.com/on which includes definitions such as “Used to indicate contact with or extent over (a surface) regardless of position” and “Used to indicate proximity”.
Regarding claim 10, Masini discloses the APD of claim 9, further comprising: a N-doped region (220) of the silicon cap layer (215+220), wherein the cathode electrode (250) is connected to the N-doped region (Fig. 2).
Regarding claim 11, Masini discloses the APD of claim 10, wherein a remaining portion (215) of the silicon cap layer (215+220) is intrinsic silicon (215) or is lighter doped than the N-doped region of the silicon cap layer (Fig. 2).
Regarding claim 12, Masini discloses the APD of claim 9, wherein the silicon layer (210) is P-doped, further comprising: an anode electrode (245) connected to the silicon layer (Fig. 2).
Regarding claim 13, Masini discloses the APD of claim 9, wherein a portion (230) of the germanium layer contacting the silicon cap layer (215+220) forms a charge layer (inherent since the claimed materials/conductivity are met; MPEP 2111 and 2112), wherein the charge layer is P-doped (Fig. 2), wherein a remaining portion (235) of the germanium layer is undoped germanium (intrinsic) or is lighter doped than the charge layer (Fig. 2).
Claims 7-8 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Masini et al. (US 7397101 B1).
Regarding claims 7 and 8, Masini fails to disclose (claim 7) the APD of claim 1, wherein a width of the silicon cap layer (215+220) is at least 500 nm and (claim 8) the APD of claim 7, wherein a thickness of the silicon cap layer (215+220) is at least 100 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at values within the claimed ranges in Masini so as to optimize device characteristics of the APD such as, for example, enhancing the internal multiplication function and/or adjusting device breakdown voltage by varying the width and thickness of the silicon cap layer.
Regarding claims 14 and 15, Masini fails to disclose (claim 14) the APD of claim 9, wherein a width of the silicon cap layer (220+215) is at least 500 nm and (claim 15) the APD of claim 14, wherein a thickness of the silicon cap layer (220+215) is at least 100 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at values within the claimed ranges in Masini so as to optimize device characteristics of the APD such as, for example, enhancing the internal multiplication function and/or adjusting device breakdown voltage by varying the width and thickness of the silicon cap layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818