DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed February 27th, 2026 are noted. Applicant’s amendments to the Specification to overcome the objections set forth in the Non-Final Office Action mailed 11/28/2025 are noted. Applicant’s amendment(s) to the Specification have overcome the objection(s) to the Title previously set forth in the Non-Final Office Action mailed 11/28/2025, so the objection(s) to the Title has been withdrawn.
Applicant’s amendment(s) to the claims have overcome the 35 U.S.C. § 112 rejection(s)
with respect to claim 5 previously set forth in the Non-Final Office Action mailed 11/28/2025, so the 35 U.S.C. § 112 rejection(s) with respect to claim 5 has been withdrawn.
Applicant’s amendment(s) to the claims have not overcome the 35 U.S.C. § 112 rejection(s)
with respect to claim 14 previously set forth in the Non-Final Office Action mailed 11/28/2025, as the amendment raises new 35 U.S.C. § 112 issues, so the 35 U.S.C. § 112 rejection(s) with respect to claim 14 has been modified and maintained. See further discussion in 35 U.S.C. 112 rejection of claim 14 below.
Applicant’s amendments to the claims are noted.
3. Claim 2 is now canceled; Claims 1 and 3-20 remain pending in the application.
4. Claims 1 and 3-20 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/03/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the first portion of each of the first and second source/drain contacts” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. There is no “a first portion of … the second source/drain contact” introduced previously in claim 14 or claim 10 on which claim 14 depends. Rather, “a second source/drain contact including a third portion” is recited in claim 10 on which claim 14 depends – establishing sufficient antecedent basis for “the third portion of the second source/drain contact” thereafter. Therefore, for the purposes of Examination, "the first portion of each of the first and second source/drain contacts” has been interpreted as --- "the first portion and the third portion, respectively, of each of the first and second source/drain contacts …” however, this edit may be altered if Applicant intends otherwise. Claim 15 is also rejected by virtue of its dependency on claim 14.
Claim 14 recites the limitation "the second portion of each of the first and second source/drain contacts” in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. There is no “a second portion of … the second source/drain contact” introduced previously in claim 14 or claim 10 on which claim 14 depends. Rather, “a second source/drain contact including … a fourth portion” is recited in claim 10 on which claim 14 depends – establishing sufficient antecedent basis for “the fourth portion of the second source/drain contact” thereafter. Therefore, for the purposes of Examination, "the second portion of each of the first and second source/drain contacts” has been interpreted as --- "the second portion and the fourth portion, respectively, of each of the first and second source/drain contacts …” however, this edit may be altered if Applicant intends otherwise. Claim 15 is also rejected by virtue of its dependency on claim 14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1, 3-6, and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ji (U.S. PG Pub No US2014/0291669A1) (of record) in view of Dorow (U.S. PG Pub No US2022/0199838A1).
Regarding claim 1, Ji teaches a semiconductor device (200B) fig. 2B [0103] comprising (refer to fig. 2B):
a substrate (210B) [0103];
a two-dimensional material layer (241B) [0103] on the substrate (210B), the two-dimensional material layer extending (241B) in a first (horizontal) direction (for the purposes of Examination, the 241B/251B material layers of Ji are all considered at least “two-dimensional” because they are three-dimensional layers comprising at least two dimensions);
a gate structure (221B) [0103] extending (comprising sidewalls of 221B extending) in a second (vertical) direction intersecting the first (horizontal) direction,
the gate structure (221B) on (bottom of) the two-dimensional material layer (241B); and
a source/drain contact (231B, 232B) [0103] on the substrate (210B), the source/drain contact (231B, 232B) (laterally) surrounding each opposing (sidewall) end of the two-dimensional material layer (241B), the source/drain contact (231B, 232B) including a first portion (P1) in (direct) contact with each opposing end of the two-dimensional material layer (241B), and the source/drain contact (231B, 232B) including a second portion (P2) on the first portion (inner sidewalls of s/d contact 231B/232B), the second portion (P2) having a larger (maximum) aspect ratio (width: height ratio) than an aspect ratio of the first portion (P1) (see annotated fig. 2B of Ji below; P2 and P1 are defined to have identical heights, but P2 is wider, hence greater aspect ratio), wherein,
the two-dimensional material layer (241B) includes a first (bottom) face extending in the first (horizontal) direction, a second (top) face opposite to the first (bottom) face, and a third (right sidewall) face extending in a third (vertical) direction perpendicular to the first (horizontal) direction, the third (right sidewall) face connecting the first (bottom) face and the second (top) face to each other.
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Annotated fig. 2B of Ji
However, Ji does not explicitly disclose the two-dimensional material layer (241B) [0103] including at least one of graphene, black phosphorous or transition metal dichalcogenide (oxide semiconductor instead),
the source/drain contact (231B, 232B) [0103] integrally surrounds the first (bottom) face, the second (top) face and the third (right sidewall) face, and
the two-dimensional material layer (241B) protrudes into the source/drain contact (231B, 232B).
Dorow teaches a semiconductor device (200) fig. 2A [0074] comprising the two-dimensional material layer (204 with 206) fig. 2A [0074] including transition metal dichalcogenide (204 formed of TMD [0074] such as WSe2 [0048] sandwiched between semiconductor oxide 206 [0071]),
the source/drain contact (210) fig. 2A [0074, 0083] integrally surrounds the first (bottom) face (of 204 with 206), the second (top) face (of 204 with 206) and the third (right sidewall) face (of 204 with 206), and
the two-dimensional material layer (204 with 206) protrudes into the source/drain contact (210).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Ji such that the (at least) two-dimensional channel material layer comprises a transition metal dichalcogenide [0074] such as WSe2 [0048] in order to improve the Young’s modulus of the 2-d semiconductor layer [0047] as well as channel mobility [0056], as taught by Dorow. Further, having the channel material protrude into the source/drain contacts offers an advantageous reduction in contact resistance [0084], as taught by Dorow.
Regarding claim 3 Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 1 above. Ji also teaches wherein the source/drain contact (231B, 232B) [0103] includes a barrier layer (first, outer layer of 131-132/231-232 [0082]) in contact with the two-dimensional material layer (241B) [0103], and the barrier layer (first, outer layer of 131-132/231-232 [0082]) includes at least one of Ti [0082].
Regarding claim 4, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 3 above. Ji also teaches wherein the source/drain contact (231B, 232B) [0103] further includes a filling film (second, inner layer of 231-232 [0082]) on the barrier layer (first, outer layer of 231-232 [0082]) (s/d contacts 131-132/231-232 may comprise multiple metal layers [0082].
Regarding claim 5, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 1 above. Ji also teaches, wherein the device (200B) further comprises an interlayer insulating film (262B) [0103] on the substrate (210B) [0103], the interlayer insulating film (262B) is on (supported by) the first portion (P1) of the source/drain contact (231B, 232B) [0103] (see annotated fig. 2B above), the first portion (P1) (defined) excluding a second portion (P2) of the source/drain contact (231B, 232B) [0103] in contact with the two-dimensional material layer (241B), and the source/drain contact (231B, 232B) [0103] is in a trench (overall gap in 262B) extending through at least a portion of the interlayer insulating film (262B).
Regarding claim 6, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 5 above. Ji also teaches wherein the trench (overall gap in 262B) fig. 2B [0103] does not extend through the two-dimensional material layer (241B) fig. 2B [0103].
Regarding claim 10, Ji teaches a semiconductor device (200B) fig. 2B [0103] comprising (refer to fig. 2B):
a substrate (210B) [0103];
a first semiconductor material layer (241B) [0103] and a second semiconductor material layer (251B) [0103] on the substrate (210B), the first semiconductor material layer (241B) spaced (vertically) apart from the second semiconductor material layer (251B) in a first (vertical) direction perpendicular to a top face of the substrate (210B), wherein each of the first (241B) and second (251B) semiconductor material layers includes a two-dimensional material (for the purposes of Examination, the 241B/251B material layers of Ji are all considered at least “two-dimensional” because they are three-dimensional layers comprising at least two dimensions);
a first gate structure (221B) [0103] on the (bottom of) first semiconductor material layer (241B) and a second gate structure (222B) [0103] on the (top of) second semiconductor material layer (251B), the first gate structure (221B) [0103] spaced apart from the second gate structure (222B) [0103] in the first (vertical) direction;
a first source/drain contact (231B) [0103] including:
a first portion (P1) and a second portion (P2) (refer to annotated fig. 2B below), the first portion (P1) surrounding one end (left, upper corner) of the first semiconductor material layer (241B), and the second portion (P2) on the first portion (P1); and
a second source/drain contact (232B) [0103] including a third portion (P3) and a fourth portion (P4), the third portion surrounding one end (right, upper corner) of the second semiconductor material layer (242B), and the fourth portion (P4) on the third portion (P3), wherein
a (max) width of the first portion (P1) is greater than a width of the second portion (P2),
a width of the third portion (P3) is greater than a width of the fourth portion (P4) (as defined in annotated fig. 2B below),
the first semiconductor layer (241B) includes a first (bottom) face extending in a horizontal direction, a second (top) face opposite to the first (bottom) face, and a third (left sidewall) face extending in a vertical direction, the third (left sidewall) face connecting the first (bottom) face and the second (top) face to each other.
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Annotated fig. 2B of Ji
However, Ji does not explicitly disclose the two-dimensional material (241B/251B) [0103] including at least one of graphene, black phosphorous or transition metal dichalcogenide (oxide semiconductor instead),
the first source/drain contact (231B) integrally surrounds the first (bottom) face, the second (top) face and the third (left sidewall) face, and
the first semiconductor material layer (241B) protrudes into the first source/drain contact (231B).
Dorow teaches a semiconductor device (200) fig. 2A [0074] comprising the two-dimensional material layer (202 with 206 and 204 with 206) fig. 2A [0074] including transition metal dichalcogenide (202 and 204 formed of TMD [0074] such as WSe2 [0048] sandwiched between semiconductor oxide 206 [0071]),
the first source/drain contact (208) fig. 2A [0074, 0083] integrally surrounds the first (bottom) face (of 204 with 206), the second (top) face (of 204 with 206) and the third (left sidewall) face (of 204 with 206), and
the first semiconductor material layer (204 with 206) protrudes into the first source/drain contact (208).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Ji such that the (at least) two-dimensional channel material layer comprises a transition metal dichalcogenide [0074] such as WSe2 [0048] in order to improve the Young’s modulus of the 2-d semiconductor layer [0047] as well as channel mobility [0056], as taught by Dorow. Further, having the channel material protrude into the source/drain contacts offers an advantageous reduction in contact resistance [0084], as taught by Dorow.
Regarding claim 11, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 10 above. Ji also teaches wherein an area (of 241B) by which the first source/drain contact (231B) fig. 2B [0103] (directly) contacts the first semiconductor material layer (241B) [0103] is different from an area by which the second source/drain contact (232B) [0103] (directly) contacts the second semiconductor material layer (251B) [0103] (second contact 232B directly contacts greater area of 251B, including top surface of 251B).
Regarding claim 12, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 10 above. Ji also teaches wherein the first source/drain contact (231B) fig. 2B [0103] includes a first barrier layer (first, outer layer of 131/231 [0082]) in contact with the first semiconductor material layer (241B) [0103], and a first filling film (second, inner layer of 231B [0082]) on the first barrier layer (first, outer layer of 231B [0082]), and the second source/drain contact (232B) [0103] includes a second barrier layer (first, outer layer of 132/232 [0082]) in contact with the second semiconductor material layer (251B) [0103], and a second filling film (second, inner layer of 232B [0082]) on the second barrier layer (first, outer layer of 232B [0082]) (s/d contacts 131-132/231-232 may comprise multiple metal layers [0082].
Regarding claim 13, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 12 above. Ji also teaches wherein the first barrier layer (first, outer layer of 231B [0082]) in surrounds a surface of one end (top, left corner) of the first semiconductor material layer (241B) [0103], and the second barrier layer (first, outer layer of 232B [0082]) surrounds a surface of one end (top, right corner) of the second semiconductor material layer (251B) [0103].
Regarding claim 14, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 10 above. Ji also teaches, wherein the device further comprises an interlayer insulating film (262B) fig. 2B [0103] on the substrate (210B) [0103], the interlayer insulating film (262B) is on (supported by) the first portion (P1) and the third portion (P3), respectively, of each of the first (231B) fig. 2B [0103] and second (232B) [0103] source/drain contacts, and the first portion (P1) is exclusive of the second portion (P2) and the fourth portion (P4), respectively, of each of the first (231B) and second (232B) [0103] source/drain contacts in contact with each of the first (241B) [0103] and second (251B) [0103] semiconductor material layers (as defined in annotated fig. 2B above),
the first source/drain contact (231B) is in a first trench (left gap between 262B and 263B) fig. 2B [0103] extending through at least a portion of the interlayer insulating film (262B), and
the second source/drain contact (232B) [0103] is in a second trench (right gap between 262B and 263B) fig. 2B [0103] extending through at least a portion of the interlayer insulating film (262B).
Regarding claim 15, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 14 above. Ji also teaches wherein a (lower, minimum) width of the first trench (left gap between 262B and 263B) fig. 2B [0103] is different from a (upper, maximum) width of the second trench (right gap between 262B and 263B) (due to slant of 263B, upper width of trenches greater than lower width of trenches, as defined in fig. 2B).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ji (U.S. PG Pub No US2014/0291669A1) (of record) modified by Dorow (U.S. PG Pub No US2022/0199838A1), as applied in claim 5 above, and further in view of Hsieh (U.S. PG Pub No US2011/0006362A1) (of record).
Regarding claim 7, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 5 above. However, Ji does not explicitly disclose wherein the trench (overall gap in 262B) fig. 2B [0103] extends through the two-dimensional material layer (241B) fig. 2B [0103].
Hsieh teaches a device [see fig. 5, 0032] wherein the trench (right gap in 125/135/140 filled by 150’, 145’) fig. 5 [0032] extends through the two-dimensional material layer (125) [0023] (at least two dimensional).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Ji such that the source-drain contact trenches extend at least partially into the channel layer [0023, 0032] in order to form a more reliable source/drain contact with reduced contact resistance and avalanche capability [0008, 0032], as taught by Hsieh.
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ji (U.S. PG Pub No US2014/0291669A1) (of record) modified by Dorow (U.S. PG Pub No US2022/0199838A1), as applied in claim 5 above, and further in view of Ando (U.S. PG Pub No US2018/0102420A1) (of record).
Regarding claim 8, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 5 above. However, Ji does not explicitly disclose wherein the device further comprises:
a lower wire structure between the substrate (210B) and the interlayer insulating film (262B); and
a lower transistor between the lower wire structure and the substrate (210B).
Ando teaches a semiconductor device [see fig. 1B, 0103] wherein the device further comprises:
a lower wire structure (comprising left 174) fig. 1B [0107] (vertically/diagonally) between the substrate (150) fig. 1B [0103] and the interlayer insulating film (219) fig. 1B [0120]; and
a lower transistor (100) fig. 1B [0103-0107] (vertically/diagonally) between the lower wire structure (left 174) and the substrate (150).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Ji such that an additional, lower transistor [0103-0107] is included in the package of Ji in order to stack the transistors to increase the degree of integration [0117] of the semiconductor package of Ji, as taught by Ando.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ji (U.S. PG Pub No US2014/0291669A1) (of record) modified by modified by Dorow (U.S. PG Pub No US2022/0199838A1), as applied in claim 1 above, and further in view of Heo (U.S. PG Pub No US2018/0151763A1) (of record).
Regarding claim 9, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 1 above. However, Ji does not explicitly disclose teaches wherein a thickness of the two-dimensional material layer (241B) [0103] is less than 5nm.
Heo teaches a semiconductor device [see fig. 11, 0105] wherein a thickness of the two-dimensional material layer (S 10) fig. 11 [0105] is less than 5nm (2D material [0074] may be about 1 nm) [0076].
`Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Ji such that the channel of the transistor(s) is/are composed of an atomically-thin 2D-material layer [0074-0076, 0105] in order to improve electrical performance and control of the semiconductor layer(s) [0074-0076, 0084, 0091-0092], as taught by Heo.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ji (U.S. PG Pub No US2014/0291669A1) (of record) in view of Ando (U.S. PG Pub No US2018/0102420A1) (of record) and Dorow (U.S. PG Pub No US2022/0199838A1).
Regarding claim 16, Ji teaches a semiconductor device (200B) fig. 2B [0103] comprising (refer to fig. 2B):
a substrate (210B) [0103];
a first transistor (comprising 221B, 231B) [0103] on the substrate (210B); and
a second transistor (comprising 222B, 251B) [0103], the second transistor (partially) in a second interlayer insulating film (262B) [0103],
wherein the second transistor (comprising 222B, 251B) includes (is included with)
a first semiconductor material layer (241B) [0103] spaced apart from a second semiconductor material layer (251B) [0103] in a vertical direction, wherein each of the first (241B) and second (251B) semiconductor material layers includes a two-dimensional material (for the purposes of Examination, the 241B/251B material layers of Ji are all considered at least “two-dimensional” because they are three-dimensional layers comprising at least two dimensions),
a first gate structure (221B) [0103] on the (bottom of) first semiconductor material layer (241B) and a second gate structure (222B) [0103] on the (top of) second semiconductor material layer (251B), wherein the first (221B) and second (222B) gate structures are spaced apart from each other in the vertical direction,
a first source/drain contact (231B) [0103] in (direct) contact with one (left) end of the first semiconductor material layer (241B), and
a second source/drain contact (232B) [0103] in (direct)) contact with one (right) end of the second semiconductor material layer (242B),
wherein each of the first (231B) and second (232B) source/drain contacts includes a first portion (P1-I/II) (see annotated fig. 2B below) in contact with one end of each of the first (241B) and second (242B) semiconductor material layers, and a second portion (P2-I/II) (see annotated fig. 2B below) on the first portion (P1), the second portion (P2-I and P2-II) having a larger aspect ratio (width: height ratio) than an aspect ratio (width: height ratio) of the first portion (P1-I and P2-II) (see annotated fig. 2B of Ji below),
the first semiconductor material layer (241B) includes a first (bottom) face extending in a horizontal direction, a second (top) face extending in a horizontal direction opposite to the first (bottom) face, and a third (left sidewall) face extending in the vertical direction, the third (left sidewall) face connecting the first (bottom) face and the second (top) face to each other.
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Annotated fig. 2B of Ji
However, Ji does not explicitly disclose a first wire structure on the first transistor (comprising 221B, 231B) [0103], the first wire structure in a first interlayer insulating film.
the two-dimensional material (241B/251B) [0103] including at least one of graphene, black phosphorous or transition metal dichalcogenide (oxide semiconductor instead),
the first source/drain contact (208) integrally surrounds the first (bottom) face, the second (top) face and the third (left sidewall) face, and
the first semiconductor material layer (241B) protrudes into the first source/drain contact (231B).
Ando teaches a semiconductor device [see fig. 1B, 0103] wherein the device further comprises:
a first wire structure (comprising left 174) fig. 1B [0107] on the first transistor (100) fig. 1B [0103], the first wire structure (left 174) in a first interlayer insulating film (upper 170) fig. 1B [0108, 0303].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Ji such that an additional, lower transistor [0103-0107] is included in the package of Ji in order to stack the transistors to increase the degree of integration [0117] of the semiconductor package of Ji, as taught by Ando.
However, Ji in view of Ando does not explicitly disclose the two-dimensional material (241B/251B) [0103] including at least one of graphene, black phosphorous or transition metal dichalcogenide (oxide semiconductor instead),
the first source/drain contact (208) integrally surrounds the first (bottom) face, the second (top) face and the third (left sidewall) face, and
the first semiconductor material layer (241B) protrudes into the first source/drain contact (231B).
Dorow teaches a semiconductor device (200) fig. 2A [0074] comprising the two-dimensional material layer (202 with 206 and 204 with 206) fig. 2A [0074] including transition metal dichalcogenide (202 and 204 formed of TMD [0074] such as WSe2 [0048] sandwiched between semiconductor oxide 206 [0071]),
the first source/drain contact (208) fig. 2A [0074, 0083] integrally surrounds the first (bottom) face (of 204 with 206), the second (top) face (of 204 with 206) and the third (left sidewall) face (of 204 with 206), and
the first semiconductor material layer (204 with 206) protrudes into the first source/drain contact (208).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistor structure of Ji such that the (at least) two-dimensional channel material layer comprises a transition metal dichalcogenide [0074] such as WSe2 [0048] in order to improve the Young’s modulus of the 2-d semiconductor layer [0047] as well as channel mobility [0056], as taught by Dorow. Further, having the channel material protrude into the source/drain contacts offers an advantageous reduction in contact resistance [0084], as taught by Dorow.
Regarding claim 17, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 16 above. Ji also teaches wherein the first source/drain contact (231B) fig. 2B [0103] is in a first trench (left gap between 262B and 263B) extending through at least a portion of the second interlayer insulating film (262B) [0103], and the second source/drain contact (232B) fig. 2B [0103] is inside a second trench (right gap between 262B and 263B) extending through at least a portion of the second interlayer insulating film (262B) [0103].
Regarding claim 18, Ji teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 16 above. Ji also teaches wherein the first source/drain contact (231B) fig. 2B [0103] includes a first barrier layer (first, outer layer of 131/231 [0082]) in contact with the first semiconductor material layer (241B) [0103], and a first filling film (second, inner layer of 231B [0082]) on the first barrier layer (first, outer layer of 231B [0082]), and
the second source/drain contact (232B) [0103] includes a second barrier layer (first, outer layer of 132/232 [0082]) in contact with the second semiconductor material layer (251B) [0103], and a second filling film (second, inner layer of 232B [0082]) on the second barrier layer (first, outer layer of 232B [0082]) (s/d contacts 131-132/231-232 may comprise multiple metal layers [0082].
Regarding claim 19, Ji in view of Ando teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 16 above. Ji in view of Ando (with reference to Ando) also teaches wherein the first transistor (100) fig. 1B [0103] includes a fin-shaped pattern (extending from 150 base in 100 zone) protruding from the substrate (150) fig. 1B [0103] in the vertical direction, and a first gate electrode (164) [0103] on the fin-shaped pattern (protrusion from 150), and the second transistor (200) fig. 1B [0103] is electrically connected to the first transistor (100) via the first wire structure (comprising left 174).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ji (U.S. PG Pub No US2014/0291669A1) (of record) modified by Ando (U.S. PG Pub No US2018/0102420A1) (of record) and Dorow (U.S. PG Pub No US2022/0199838A1), as applied in claim 16 above, and further in view of Sharma (U.S. PG Pub No US 2022/0416034 A1) (of record).
Regarding claim 20, Ji in view of Ando teaches the semiconductor device (200B) fig. 2B [0103] as discussed in claim 16 above. Ji in view of Ando (with reference to Ando) also teaches wherein the second transistor (200) fig. 1B [0103 Ando] is electrically connected to the first transistor (100) fig. 1B [0103] via the first wire structure (left 174) fig. 1B [0103].
However, does not explicitly disclose
wherein the first transistor (100) includes a nanosheet, and a second gate electrode surrounding the nanosheet.
Sharma teaches a device [see figs. 11-13, 0084-0087] wherein the first transistor (700A) fig. 12 [0085] includes a nanosheet (204) [0044] (nanosheet/nanoribbon [0029]), and a second gate electrode (212) fig. 11 [0062] surrounding the nanosheet (204) (see fig. 13 for implementation of transistor 700A in plurality).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package device of Ji in view of Ando such that an additional, gate all around nanosheet transistor is provided [0027-0028, 0084-0087] in order to increase the flexibility of the possible electrical configurations of the package [0027] for more applications [0028], as taught by Sharma.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 3-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
All references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they feature multiple, spaced transistors.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 04/07/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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