DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 15-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/09/2025. Claim 18-25 have been canceled and new claims 26-33 have been added as per the reply filed on 04/13/2026.
Claims 1-14 and 26-33 are still pending.
Response to Amendment
The amendment filed on 04/13/2026 has been accepted and entered. Claims 1-14 and 26-33 remain pending in this application. Applicant’s amendments to the Specification, Drawing, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed on 01/30/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 27 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claim 27, the claim 27 limitation "wherein the second spacer layers each include a void." in Lines L1-2 is broader in scope than the independent claim 26 limitation “wherein the second spacer layers each include a void located at a level corresponding to a respective one of the conductive layers” in Lines L10-11, so the claim 27 limitation "wherein the second spacer layers each include a void." in Lines L1-2, fails to further limit the subject matter of independent claim 26.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 26-28, and 32-33 is/are rejected under 35 U.S.C. 1102(a)(1) as being anticipated by Lee et al. (US20190312052A1-Lee52).
Regarding claims 26 and 27, Lee52 discloses a semiconductor device comprising:
a gate structure (Examiner's annotated Fig 2) including
insulating layers (ILD-Fig 2) and
conductive layers (GE-Fig 2) that are alternately stacked (insulating layers ILD and conductive layers GE being alternatively stacked-Fig 2);
a contact plug extending in a stacking direction of the insulating layers through the gate structure (Contact plug CSP extending in the stacking direction of the insulating layers ILD through the gate structure-Examiner's annotated Fig 2);
first spacer layers each located between the conductive layers and the contact plug (First spacer layers SS Left located between the conductive layers 154 and the contact plug CSP-Examiner's annotated Fig 18A); and
second spacer layers each located between the contact plug and the first spacer layers (Second spacer layers SS Right located between the First spacer layers and the contact plug CSP-Examiner's annotated Fig 18),
wherein the second spacer layers each include a void located at a level corresponding to a respective one of the conductive layers (Second spacer layers SS Right located between the First spacer layers SS left and the contact plug CSP, including a void AG, located at a level on top of so at a level corresponding to a respective one of the conductive layers 154-Examiner's annotated Fig 18A).).
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Regarding claim 28, Lee52 discloses all the elements of claim 26, as noted above.
Lee52 further discloses a semiconductor device
wherein the first spacer layers are void-free oxide layers (First spacer layers SS Left are void-free oxide layers-Examiner's annotated Fig 2, [046] L26, [033] L26-27).
Regarding claim 32, Lee52 discloses all the elements of claim 26, as noted above.
Lee52 further discloses a semiconductor device
wherein the first spacer layers located at different levels have different thicknesses (First spacer layers SS Left having different thickness at different levels-Examiner's annotated Fig 18A).
Regarding claim 33, Lee52 discloses all the elements of claim 26, as noted above.
Lee52 further discloses a semiconductor device
wherein the second spacer layers located at different levels have different thicknesses (second spacer layers SS Right having different thickness at different levels-Examiner's annotated Fig 18A)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17).
Regarding claim 1, Lee52 discloses a semiconductor device comprising:
a gate structure (Examiner's annotated Fig 2) including
insulating layers (ILD-Fig 2) and
conductive layers (GE-Fig 2) that are alternately stacked (insulating layers ILD and conductive layers GE being alternatively stacked-Fig 2);
a contact plug extending in a stacking direction of the insulating layers through the gate structure (Contact plug CSP extending in the stacking direction of the insulating layers ILD through the gate structure-Examiner's annotated Fig 2);
first spacer layers each located between the conductive layers and the contact plug (First spacer layers SS Left located between the conductive layers 154 and the contact plug CSP-Examiner's annotated Fig 18A); and
second spacer layers each located between the contact plug and the first spacer layers (Second spacer layers SS Right located between the First spacer layers and the contact plug CSP-Examiner's annotated Fig 18).
Lee52 does not disclose a semiconductor device comprising
first spacer layers spaced apart from one another in the stacking direction; and
second spacer layers each spaced apart from one another in the stacking direction.
Yao17 teaches a semiconductor device comprising
first spacer layers spaced apart from one another in the stacking direction (first spacer layers 216 spaced apart by semiconductor layers 204a from one another in the vertical/stacking direction-Fig 8); and
second spacer layers each spaced apart from one another in the stacking direction (second spacer layers 216/218 each spaced apart from one another by semiconductor layers 204a in the vertical/stacking direction-Fig 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 as taught by Yao17 for the purpose of selecting the compositions of the spacer layers 216 and 220 to enhance device performance in terms of improved etching resistance, reduced parasitic capacitance, and greater design freedom (Yao17:[0037]).
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Regarding claim 2, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the second spacer layers each include a void (Second spacer layers located between the First spacer layers and the contact plug CSP, including a void AG-Examiner's annotated Fig 18A).
Regarding claim 3, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the first spacer layers are void-free oxide layers (First spacer layers SS Left are void-free oxide layers-Examiner's annotated Fig 2, [046] L26, [033] L26-27).
Regarding claim 4, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein at least one of the first spacer layers and the second spacer layers includes silicon oxide. (first and second spacers layers SS include silicon oxide layer-[033]L26-27).
Regarding claim 9, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
further comprising: barrier layers (barrier layers 152-Examiner's annotated Fig 18A) located between the conductive layers and the first spacer layers, respectively (barrier layers 152 located between the conductive layers 154 and the first spacers SS left-Examiner's annotated Fig 18A).
Regarding claim 10, Lee52 and Yao17 combination discloses all the elements of claim 9, as noted above.
Lee52 further discloses a semiconductor device
wherein the barrier layers each include oxide or nitride (barrier layers 152 include nitride-[0038] L3-6).
Regarding claim 11, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the first spacer layers located at different levels have different thicknesses (First spacer layers SS Left having different thickness at different levels-Examiner's annotated Fig 18A).
Regarding claim 12, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the second spacer layers located at different levels have different thicknesses (second spacer layers SS Right having different thickness at different levels-Examiner's annotated Fig 18A).
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17), and further in view of Lee et al. (US20210098367A1-Lee67).
Regarding claim 5, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 and Yao17 combination does not disclose a semiconductor device
wherein the contact plug includes a pillar and a first protrusion protruding from the pillar.
Lee67 teaches a semiconductor device
wherein the contact plug includes a pillar and a first protrusion protruding from the pillar (Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 in view of Yao17 as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
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Regarding claim 6, Lee52, Yao17, and Lee67 combination teaches all the elements of claim 5, as noted above.
Lee67 further teaches a semiconductor device
wherein the gate structure includes a step structure for exposing at least one of the conductive layers (Gate structure 100 includes a step structure for exposing the uppermost conductive layers 331-Examiner's annotated Fig 5), and
the pillar passes through an uppermost conductive layer exposed by the step structure (Pillar of Contact Plug 333 passing through the uppermost conductive layer-Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 in view of Yao17, as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
Regarding claim 7, Lee52, Yao17, and Lee67 combination teaches all the elements of claim 6, as noted above.
Lee67 further teaches a semiconductor device
wherein the first protrusion is connected to a top surface of the uppermost conductive layer exposed by the step structure (Uppermost conductive layer 331 connected to the top surface of First protrusion-Examiner's annotated Fig 5, [0060] L 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 in view of Yao17, as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17), and further in view of Tsutsumi et al. (US20160163728A1-Tsutsumi28).
Regarding claim 13, Lee52 and Yao17 combination discloses all the elements of claim 1, as noted above.
Lee52 and Yao17 combination does not disclose a semiconductor device
further comprising: sacrificial layers located between the first spacer layers and the conductive layers, respectively.
Tsutsumi28 teaches a semiconductor device
further comprising: sacrificial layers (sacrificial layers 52 residuals could be present following the backside recesses 43 formation. The backside recesses 43 are then filled with a conductive material 46 so the sacrificial layers 52 residuals would be located between the first spacer 51 and the conductive layers 46-Fig 4, Fig 5A, Fig 6C, [0077] L1-8) located between the first spacer layers and the conductive layers, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 in view of Yao17, as taught by Tsutsumi28 for the purpose of eliminating the over etch damage to the spacers 51 (Tsutsumi28: [0008], [0024] L15-24).
Regarding claim 14, Lee52, Yao17, and Tsutsumi28 combination discloses all the elements of claim 13, as noted above.
Tsutsumi28 further teaches a semiconductor device
wherein the sacrificial layers each include amorphous silicon (Sacrificial layers 52 can include amorphous silicon-[0077] L1-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 in view of Yao17, as taught by Tsutsumi28 for the purpose of eliminating the over etch damage to the spacers 51 (Tsutsumi28: [0008], [0024] L15-24).
Claim(s) 29-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Lee et al. (US20210098367A1-Lee67).
Regarding claim 29, Lee52 discloses all the elements of claim 26, as noted above.
Lee52 does not disclose a semiconductor device
wherein the contact plug includes a pillar and a first protrusion protruding from the pillar.
Lee67 teaches a semiconductor device
wherein the contact plug includes a pillar and a first protrusion protruding from the pillar (Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
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Regarding claim 30, Lee52 and Lee67 combination teaches all the elements of claim 29, as noted above.
Lee67 further teaches a semiconductor device
wherein the gate structure includes a step structure for exposing at least one of the conductive layers (Gate structure 100 includes a step structure for exposing the uppermost conductive layers 331-Examiner's annotated Fig 5), and
the pillar passes through an uppermost conductive layer exposed by the step structure (Pillar of Contact Plug 333 passing through the uppermost conductive layer-Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52, as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
Regarding claim 31, Lee52 and Lee67 combination teaches all the elements of claim 30, as noted above.
Lee67 further teaches a semiconductor device
wherein the first protrusion is connected to a top surface of the uppermost conductive layer exposed by the step structure (Uppermost conductive layer 331 connected to the top surface of First protrusion-Examiner's annotated Fig 5, [0060] L 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52, as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art of record does not teach or suggest a semiconductor device , namely “further comprising: a second protrusion located in the second spacer layers and protruding from the pillar”.
References such as Lee et al. (US20190312052A1-Lee52), Yao et al. (US20210234017A1-Yao17), and Lee et al. (US20210098367A1-Lee67) combination, teaches a semiconductor device, but does not teach or suggest a semiconductor device, namely “further comprising: a second protrusion located in the second spacer layers and protruding from the pillar”, in combination with other claimed elements.
Response to Arguments
Applicant’s arguments see pages 9-17 of Remarks, filed on 04/13/2026 with respect to the 35 U.S.C 102 rejection of claims 1-14 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claims 1 and 4 been amended to further define the claimed subject matter see pages 5-8 of Amendments to Claims, filed on 04/13/2026.
Claim(s) 1-4 and 9-12is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17), as described above.
Therefore, claim(s) 1-4 and 9-12 stand rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17).
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17), and further in view of Lee et al. (US20210098367A1-Lee67), as described above.
Therefore, claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17), and further in view of Lee et al. (US20210098367A1-Lee67).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17), and further in view of Tsutsumi et al. (US20160163728A1-Tsutsumi28), as described above.
Therefore, claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Yao et al. (US20210234017A1-Yao17), and further in view of Tsutsumi et al. (US20160163728A1-Tsutsumi28).
Claim(s) 29-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Lee et al. (US20210098367A1-Lee67), as described above.
Therefore, claim(s) 29-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Lee et al. (US20210098367A1-Lee67).
Claim(s) 26-28, and 32-33 is/are rejected under 35 U.S.C. 1102(a)(1) as being anticipated by Lee et al. (US20190312052A1-Lee52), as described above.
Therefore, claim(s) 26-28, and 32-33 is/are rejected under 35 U.S.C. 1102(a)(1) as being anticipated by Lee et al. (US20190312052A1-Lee52).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US20210174839A1-Lee39) teaches a semiconductor device wherein the contact plug includes a pillar and a first protrusion protruding from the pillar (Fig 5D).
Hinoue et al. (US 20220406794 A1-Hinoue94) teaches a semiconductor device wherein the second spacer includes a void (Fig 14).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/ Examiner, Art Unit 2812 05/04/2026
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812
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