DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 15-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/09/2025.
Claims 1-14 are still pending.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the second protrusion must be shown or the feature(s) canceled from the claim(s). Fig 2D does not clearly show what corresponds to the second protrusion 260C.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the limitation "wherein the first spacer layers or the second spacer layers each include silicon oxide" in Lines L1-2, renders the claim indefinite because it is unclear if only one of the first spacer layer and the second layer spacers, or both of them should include silicon oxide. In the purpose of compact prosecution, “wherein the first spacer layers or the second spacer layers each include silicon oxide" has been interpretated as "wherein the first spacer layers or the second spacer layers .
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 9-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US20190312052A1-Lee52).
Regarding claim 1, Lee52 discloses a semiconductor device comprising:
a gate structure (Examiner's annotated Fig 2) including
insulating layers (ILD-Fig 2) and
conductive layers (GE-Fig 2) that are alternately stacked (insulating layers ILD and conductive layers GE being alternatively stacked-Fig 2);
a contact plug extending in a stacking direction of the insulating layers through the gate structure (Contact plug CSP extending in the stacking direction of the insulating layers ILD through the gate structure-Examiner's annotated Fig 2);
first spacer layers each located between the conductive layers and the contact plug (First spacer layers SS Left located between the conductive layers 154 and the contact plug CSP-Examiner's annotated Fig 18A); and
second spacer layers each located between the contact plug and the first spacer layers (Second spacer layers SS Right located between the First spacer layers and the contact plug CSP-Examiner's annotated Fig 18).
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Regarding claim 2, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the second spacer layers each include a void (Second spacer layers located between the First spacer layers and the contact plug CSP, including a void AG-Examiner's annotated Fig 18A).
Regarding claim 3, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the first spacer layers are void-free oxide layers (First spacer layers SS Left are void-free oxide layers-Examiner's annotated Fig 2, [046] L26, [033] L26-27).
Regarding claim 4, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the first spacer layers or the second spacer layers each include silicon oxide (first/second spacers layers SS include silicon oxide layer-[033]L26-27).
Regarding claim 9, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
further comprising: barrier layers (barrier layers 152-Examiner's annotated Fig 18A) located between the conductive layers and the first spacer layers, respectively (barrier layers 152 located between the conductive layers 154 and the first spacers SS left-Examiner's annotated Fig 18A).
Regarding claim 10, Lee52 discloses all the elements of claim 9, as noted above.
Lee52 further discloses a semiconductor device
wherein the barrier layers each include oxide or nitride (barrier layers 152 include nitride-[0038] L3-6).
Regarding claim 11, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the first spacer layers located at different levels have different thicknesses (First spacer layers SS Left having different thickness at different levels-Examiner's annotated Fig 18A).
Regarding claim 12, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 further discloses a semiconductor device
wherein the second spacer layers located at different levels have different thicknesses (second spacer layers SS Right having different thickness at different levels-Examiner's annotated Fig 18A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Lee et al. (US20210098367A1-Lee67).
Regarding claim 5, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 does not disclose a semiconductor device
wherein the contact plug includes a pillar and a first protrusion protruding from the pillar.
Lee67 teaches a semiconductor device
wherein the contact plug includes a pillar and a first protrusion protruding from the pillar (Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
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Regarding claim 6, Lee52 and Lee67 combination teaches all the elements of claim 5, as noted above.
Lee52 does not disclose a semiconductor device
wherein the gate structure includes a step structure for exposing at least one of the conductive layers, and
the pillar passes through an uppermost conductive layer exposed by the step structure.
Lee67 further teaches a semiconductor device
wherein the gate structure includes a step structure for exposing at least one of the conductive layers (Gate structure 100 includes a step structure for exposing the uppermost conductive layers 331-Examiner's annotated Fig 5), and
the pillar passes through an uppermost conductive layer exposed by the step structure (Pillar of Contact Plug 333 passing through the uppermost conductive layer-Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
Regarding claim 7, Lee52 and Lee67 combination teaches all the elements of claim 6, as noted above.
Lee52 does not disclose a semiconductor device
wherein the first protrusion is connected to a top surface of the uppermost conductive layer exposed by the step structure.
Lee67 further teaches a semiconductor device
wherein the first protrusion is connected to a top surface of the uppermost conductive layer exposed by the step structure (Uppermost conductive layer 331 connected to the top surface of First protrusion-Examiner's annotated Fig 5, [0060] L 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 as taught by Lee67 for the purpose of improving connections between local lines of the memory blocks to peripheral circuit (Lee67: [0008], [0024] L1-5).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20190312052A1-Lee52) in view of Tsutsumi et al. (US20160163728A1-Tsutsumi28).
Regarding claim 13, Lee52 discloses all the elements of claim 1, as noted above.
Lee52 does not disclose a semiconductor device
further comprising: sacrificial layers located between the first spacer layers and the conductive layers, respectively.
Tsutsumi28 teaches a semiconductor device
further comprising: sacrificial layers (sacrificial layers 52 residuals could be present following the backside recesses 43 formation. The backside recesses 43 are then filled with a conductive material 46 so the sacrificial layers 52 residuals would be located between the first spacer 51 and the conductive layers 46-Fig 4, Fig 5A, Fig 6C, [0077] L1-8) located between the first spacer layers and the conductive layers, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 as taught by Tsutsumi28 for the purpose of eliminating the over etch damage to the spacers 51 (Tsutsumi28: [0008], [0024] L15-24).
Regarding claim 14, Lee52 and Tsutsumi28 combination discloses all the elements of claim 13, as noted above.
Tsutsumi28 further teaches a semiconductor device
wherein the sacrificial layers each include amorphous silicon (Sacrificial layers 52 can include amorphous silicon-[0077] L1-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lee52 as taught by Tsutsumi28 for the purpose of eliminating the over etch damage to the spacers 51 (Tsutsumi28: [0008], [0024] L15-24).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art of record does not teach or suggest a semiconductor device , namely “further comprising: a second protrusion located in the second spacer layers and protruding from the pillar”.
References such as Lee et al. (US20190312052A1-Lee52) and Lee et al. (US20210098367A1-Lee67) combination, teaches a semiconductor device, but does not teach or suggest a semiconductor device, namely “further comprising: a second protrusion located in the second spacer layers and protruding from the pillar”, in combination with other claimed elements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US20210174839A1-Lee39) teaches a semiconductor device wherein the contact plug includes a pillar and a first protrusion protruding from the pillar (Fig 5D).
Yao et al. (US20210234017A1-Yao17) teaches a semiconductor device wherein the second spacer layers each include a void (Fig 8).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 01/12/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812