DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 5/16/23, 4/5/24, and 12/19/25. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Specification
The title of the invention is not descriptive as it is generic. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the term "substantially" in claim 4 is a relative term which renders the claim indefinite. The term "substantially" is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term substantial is defined as “being largely but not wholly that which is specified.” The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” near the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (U.S. 2016/0307837 A1; “Park”).
Regarding claim 21, Park discloses a semiconductor device, comprising:
A first transistor including a first channel structure (portion of 100 under G1, Fig. 3A) on a substrate (100, Fig. 3A), a first gate structure (G1, GI, SL1) extending in a second direction parallel to a surface of the substrate to cover the first channel structure (portion of 100 under G1, Fig. 3A), and a first impurity region structure (SD on both sides of G1, Fig. 3A) on both sides of the first gate structure (G1, GI, SL1) in a first direction perpendicular to the second direction, wherein the first impurity region structure (SD on both sides of G1, Fig. 3A) is connected to the first channel structure (portion of 100 under G1, Fig. 3A), and has a first volume; and
A buffer transistor including a second channel structure (portion of 100 under G2, Fig. 3A) on the substrate (100, Fig. 3A), a second gate structure (G2, GI, SL2, Fig. 3A) extending in the second direction to cover the second channel structure (portion of 100 under G2, Fig. 3A), and a second impurity region structure (SD between G2 and G3, Fig. 3A) on a side of the second gate structure (G2, GI, SL2) in the first direction to be connected with the second channel structure (portion of 100 under G2, Fig. 3A),
Wherein the second impurity region structure (SD between G2 and G3, Fig. 3A) has a second volume different from the first volume of the first impurity region structure (SD on both sides of G1, Fig. 3A) ([0076]), and
Wherein the first impurity region structure (SD on side of G1, Fig. 3A) contacts the other side of the second gate structure (G2, GI, SL2, Fig. 3A) in the first direction.
Allowable Subject Matter
Claims 1, 3, and 5-19 are allowed.
Claim 1 contains allowable subject matter because of the limitation of a second impurity region structure between second channel structures, the second impurity region structure connecting sidewalls of adjacent second channel structures, and having a second volume smaller than the first volume; a third impurity region structure between the first and second channel structures, the third impurity region structure connecting sidewalls of adjacent first and second channel structures, and having a third volume smaller than the first volume and greater than the second volume; and a plurality of gate structures disposed between the first to third impurity region structures, respectively, each of the gate structure covering one of the first and second channel structures, and extending in the second direction. Claims 3 and 5-12 depend on claim 1.
Claim 13 contains allowable subject matter because of the limitation of a second transistor on the substrate, the second transistor including a second channel structure having a second width in the second direction less than the first width, a second gate structure extending in the second direction to cover the second channel structure, and a second impurity region structure on both sides of the second gate structure in the first direction, wherein the second impurity region structure is connected to the second channel structure, and has a second volume smaller than the first volume; and a buffer transistor on the substrate, the buffer transistor including a third channel structure between the first and second transistors, a third gate structure extending in the second direction to cover the third channel structure, a third impurity region structure on a side of the third gate structure in the first direction connected to the third channel structure, and a fourth impurity region structure on another side of the third gate structure connected to the third channel structure, wherein the fourth impurity region structure has a volume different from a volume of the third impurity region structure. Claims 14-19 depend on claim 13.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 12/12/2025