DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 3/2/2026 have been entered and considered. The amendment to claim 20 is acknowledged and the rejection of the claim under 35 U.S.C. 112(b) is hereby withdrawn.
Response to Arguments
Applicant's arguments filed 3/2/2026 have been fully considered but they are not persuasive. Applicant alleges that the “redistribution layer 109” in Jiang is a separate and distinct component that cannot be relied on to provide a feature that the “copper pillar 102” does not include. The examiner disagrees for the following reasons:
Even though it is referred to as a “redistribution layer 109” that extends in a horizontal direction, it still constitutes part of the “copper structure 112” that also extends in a vertical direction as “copper pillar 102” does. The examiner considers this portion of the “copper structure 112” as a composite pillar structure with a lower base having a different width that an upper portion of the pillar.
Applicant further alleges that Choi does not cure the deficiencies of Jiang in regards to the plurality of circuit devices on a second side of the first substrate opposite the first side; applicant states that “substrate 101” in Jiang is an “integrated circuit” whereas the “TSV interposer 178” of Choi is, by definition, an interposer and not an “integrated circuit”. The examiner disagrees for the following reasons:
“TSV interposer 178” comprises “TSVs 176” and a “redistribution layer 220” that transmit signals, such that they can be considered circuit elements of the “TSV interposer 178”. Choi is relied upon to teach that circuit devices and/or passive elements can exist on both sides of a substrate. “Substrate 101” and “TSV interposer 178” both act as substrates onto which other devices are bonded.
The rejections of claims 1, 14, and 19 are sustained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang US 20160351520 A1 (hereinafter referred to as Jiang), in view of Choi et al. US 20150171024 A1 (hereinafter referred to as Choi).
Regarding claim 1, Jiang teaches
An integrated circuit (IC) chip (“IC chip 100” para. 0014 FIG. 1) comprising: a plurality of bump interconnects (“copper structure 112” with “copper seed layer 106” and “metal pads 103”, para. 0016) on a first side of a first substrate (top side of “substrate 101” para. 0015); and
a plurality of circuit devices (“electrical circuits” in “substrate 101”, para. 0014), a second side of the first substrate (lower surface of “substrate 101”) opposite the first side in a first direction; wherein: the plurality of bump interconnects electrically coupled to at least one circuit device among the plurality of circuit devices (“Electrical circuits fabricated in the substrate 101 may be connected to an electrical circuit external to the IC chip 100 by way of a plurality of metal pads 103”, para. 0014, and “copper structures 112” are formed on the “metal pads 112” for external connection, para. 0015-0016. As such, “electrical circuits” are connected to “copper structures 112”.); and each bump interconnect of the plurality of bump interconnects comprises:
a metal pad (“metal pads 103”);
a conductive pillar (“copper structure 112” with “copper seed layer 106”) comprising a first end (top end with “solder bump 105”, para. 0015) and a second end (end nearest “metal pad 103”) opposite the first end in the first direction;
a solder (“solder bump 105”) on the first end of the conductive pillar; and
the second end of the conductive pillar comprising a plurality of surfaces (surfaces of “copper seed layer 106” in “micro-vias 201” formed through “passivation layer 104”, para. 0019 FIG. 1-3) in contact with the metal pad in respective contact areas (“copper seed layer 106” contacts “metal pad 103” through the “micro-vias 201”, para. 0020 FIG. 1 and 4-5).
However, Jiang fails a plurality of circuit devices on a second side of the first substrate (209) opposite the first side in a first direction.
Nevertheless, Choi teaches
a plurality of circuit devices and/or passive elements (“plurality of semiconductor die or components 124” para 0037 FIG. 5) on a second side of the first substrate (top surface of “TSV interposer 178”, para. 0048) opposite the first side (bottom surface of “TSV interposer 178”) in a first direction.
Jiang and Choi teach substrates with bump interconnects. The “substrate 101” in Chen has circuitry within (Chen para. 0014). Meanwhile, “TSV interposer 178” in Choi incudes “die 124” on a side opposite to the bump interconnects comprised of “bumps 226” on “conductive layers 220” (Choi para. 0070). The “TSV interposer 178” in Choi enables different “die 124” with smaller pitched “pillars 158” to be integrated into a package with connections at a pitch of “bumps 226”. “Die 124” may have different type of circuit elements (para. 0038). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the first substrate can be an interposer such as “TSV interposer 178” so that a plurality of smaller circuit devices can be integrated into a larger package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip in Chen with the substrate and circuit devices in Choi. With an interposer substrate, a plurality of circuit devices can be interconnected to become part of a package.
Regarding claim 2, Jiang, modified by Choi, teach the IC of claim 1, each bump interconnect further comprising: a passivation layer (“passivation layer 104” para. 0019) disposed around and isolating each of the plurality of surfaces of the second end of the conductive pillar (portions of “passivation layer 104” are around the “micro-vias 201”, FIG. 1-2).
Regarding claim 3, Jiang, modified by Choi, teach the IC of claim 1, each bump interconnect further comprising: a passivation layer (“passivation layer 104”) disposed between, in the first direction, a perimeter of the second end of the conductive pillar and the metal pad (a portion of “passivation layer 104” is between the perimeter of “copper structure 112” and “metal pad 103”, illustrated in FIG. 1 below).
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Regarding claim 4, Jiang, modified by Choi, teach the IC of claim 2, wherein: the passivation layer comprises openings (“micro-vias 201” as seen in FIG. 2) corresponding to each of the plurality of surfaces of the second end of the conductive pillar; and each of the plurality of surfaces extends through the openings to contact the metal pad in the contact areas (“copper seed layer 106” and lower portion of “copper structure 112” extend through the micro-vias to contact “metal pad 103”, para. 0015).
Regarding claim 6, Jiang, modified by Choi, teach the IC of claim 1, wherein: the plurality of surfaces comprises a uniform pattern of end surfaces of the second end of the conductive pillar (the plurality of surfaces of “copper seed layer 106” through the vias appear substantially uniform in FIG. 1).
Regarding claim 10, Jiang, modified by Choi, teach the IC of claim 1, wherein: the plurality of surfaces comprises at least four (4) surfaces (FIG. 1 shows six surfaces of “copper seed layer 106” in contact with “metal pad 103”).
Regarding claim 12, Jiang, modified by Choi, teach the IC of claim 2, wherein: the passivation layer is disposed at a center of a cross-section of the second end of the conductive pillar (FIG. 1 shows a portion of “passivation layer 104” in a substantially central region under the “copper structure 112”).
Regarding claim 13, Jiang, modified by Choi, teaches the IC of claim 1 but fails to expressly teach the IC of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
Nevertheless, Choi teaches that “semiconductor package 240” can be connected to a PCB (para. 0073). Semiconductor packages can be mounted on a PCB such as “PCB 52” to form an “electronic device 50” (para. 0028-0029 FIG. 1). “Electronic device 50” can be part of “a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device” or can be a “graphics card, network interface card, or other signal processing card that can be inserted into a computer” (para. 0029). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “semiconductor package 240” can be part of an “electronic device 50” used for many different purposes, such as cellular phone, a PDA, or a signal processor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the IC chip taught between Jiang and Choi. The IC chip can be integrated into a cellular phone, a PDA, or a signal processor in a computer.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang US 20160351520 A1 (hereinafter referred to as Jiang), in view of Choi et al. US 20150171024 A1 (hereinafter referred to as Choi).
Regarding claim 14, Jiang, teaches
A method of fabricating an integrated circuit (IC) (method of forming “IC chip 100” para. 0014 FIG. 1) comprising:
forming a plurality of circuit devices (“electrical circuits” in “substrate 101”, para. 0014),
a second side of a first substrate (lower surface of “substrate 101”); and
forming a plurality of bump interconnects (“copper structure 112” with “copper seed layer 106” and “metal pads 103”, para. 0016) on a first side of the first substrate (top side of “substrate 101” para. 0015) opposite in a first direction to the second side of the substrate and electrically coupled to first circuit devices among the plurality of circuit devices (“Electrical circuits fabricated in the substrate 101 may be connected to an electrical circuit external to the IC chip 100 by way of a plurality of metal pads 103”, para. 0014, and “copper structures 112” are formed on the “metal pads 112” for external connection, para. 0015-0016. As such, “electrical circuits” are connected to “copper structures 112”.), each bump interconnect of the plurality of bump interconnects comprising:
a metal pad (“metal pads 103”);
a conductive pillar (“copper structure 112” with “copper seed layer 106”) comprising a first end (top end with “solder bump 105”, para. 0015) and a second end (end nearest “metal pad 103”) opposite the first end in the first direction;
a solder (“solder bump 105”) on the first end of the conductive pillar; and
the second end of the conductive pillar comprising a plurality of surfaces (surfaces of “copper seed layer 106” in “micro-vias 201” formed through “passivation layer 104”, para. 0019 FIG. 1-3) in contact with the metal pad in respective contact areas.
However, Jiang fails to teach forming the plurality of circuit devices on a second side of a first substrate
Nevertheless, Choi teaches
Forming the plurality of circuit devices and/or passive elements (“plurality of semiconductor die or components 124” para 0037 FIG. 5) on a second side of the first substrate (top surface of “TSV interposer 178”, para. 0048) opposite the first side (bottom surface of “TSV interposer 178”) in a first direction.
Jiang and Choi teach substrates with bump interconnects. The “substrate 101” in Chen has circuitry within (Chen para. 0014). Meanwhile, “TSV interposer 178” in Choi incudes “die 124” on a side opposite to the bump interconnects comprised of “bumps 226” on “conductive layers 220” (Choi para. 0070). The “TSV interposer 178” in Choi enables different “die 124” with smaller pitched “pillars 158” to be integrated into a package with connections at a pitch of “bumps 226”. “Die 124” may have different type of circuit elements (para. 0038). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the first substrate can be an interposer such as “TSV interposer 178” so that a plurality of smaller circuit devices can be integrated into a larger package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip in Chen with the substrate and circuit devices in Choi. With an interposer substrate, a plurality of circuit devices can be interconnected to become part of a package.
Regarding claim 15, Jiang, modified by Choi, teach the method of claim 14, wherein forming the plurality of bump interconnects comprises, for each bump interconnect of the plurality of bump interconnects (“copper structure 112” with “copper seed layer 106” and “metal pads 103”), forming the metal pad on the first side of the first substrate (as modified, the substrate is “TSV interposer 178” from Choi. “Metal pads 103” are formed on the lower surface analogous to the “conductive layer 220”.) and coupled to a circuit device of the plurality of circuit devices on the second side of the substrate (in place of “conductive layer 220”, “metal pads 103” on bottom of “TSV interposer 178” connect to “dies 124”, para. 0068).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang, modified by Choi, in view of Sawai et al. US 20030080421 A1 (hereinafter referred to as Sawai).
Jiang, modified by Choi, teach the method of claim 15 but fail to teach wherein forming each of the plurality of bump interconnects further comprises: forming a first passivation mask on the first side of the first substrate; and forming a hard passivation layer comprising openings to the metal pad based on the first passivation mask.
Nevertheless, Sawai teaches
wherein forming each of the plurality of bump interconnects further comprises: forming a first passivation mask on the first side of the first substrate (para. 0055 describes a photo mask being used); and
forming a hard passivation layer comprising openings to the metal pad based on the first passivation mask (“protective film 14” is patterned with the photo mask to form “openings 15” on “pad 13”, para. 0055-0056).
Jiang, modified by Choi, and Sawai teach conductive pillars formed over a patterned passivation layer. Jiang does not specify the steps in forming the “micro-vias 201” in “passivation layer 104”. In Sawai, the “openings 15” in the silicon nitride “protective film 14” are formed through etching with use of a mask (para. 0054-0055). The “openings 15” can have small sizes such as 5 microns and be arranged in a grid pattern (para. 0043 and 0056). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a mask is suitable to pattern the “protective film 14” with small openings in a uniform pattern.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an IC chip taught between Jiang and Choi with the patterning steps taught in Sawai. A mask is known to be used for patterning small openings in a passivation layer.
Claims 19-22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. US 20160027717 A1 (hereinafter referred to as Jang), in view of Jiang US 20160351520 A1 (hereinafter referred to as Jiang), further in view of Choi et al. US 20140312512 A1 (hereinafter referred to as Choi’512), Shin et al. US 20100230811 A1 (hereinafter referred to as Shin), and Sawai et al. US 20030080421 A1 (hereinafter referred to as Sawai).
Regarding claim 19, Jang teaches
An integrated circuit (IC) package (“integrated circuit (IC) assembly 200” para. 0027 FIG. 2), comprising:
a first substrate (“package substrate 121” para. 0027);
a plurality of bump interconnects (“solder balls 112” and “pads 110” on “package substrate 121”, para. 0034) on a first side of the first substrate (bottom of “package substrate 121”), each bump interconnect comprising:
a metal pad (“pad 110”);
a second substrate (“circuit board 122” para. 0034) comprising a plurality of contact pads (“pads 110” on “circuit board 122”, para. 0034), each coupled to one of the plurality of bump interconnects (“first pads 110a” are connected to “solder balls 112” and “pads 110”);
a plurality of circuit devices (“IC assembly 200 may include one or more dies (hereinafter “die 102”) electrically and/or physically coupled with a package substrate 121”, para. 0027) on a second side of the first substrate opposite to the first end in a first direction (top side of “package substrate 121”); and
the plurality of bump interconnects electrically coupled to at least one of the plurality of circuit devices and to the second substrate (“interconnects 106” under “die 102” are routed to “pads 110” on “package substrate 121”, para. 0034).
However, Jang fails to teach a conductive pillar comprising a first end and a second end opposite to the first end in a first direction; a solder on the first end of the conductive pillar; and a plurality of surfaces at the second end of the conductive pillar in contact with the metal pad in a plurality of respective contact areas; the plurality of contact pads, each coupled to the solder of a corresponding one of the plurality of bump interconnects.
Nevertheless, Jiang teaches
a conductive pillar (“copper structure 112” with “copper seed layer 106”) comprising a first end (top end with “solder bump 105”, para. 0015) and a second end (end nearest “metal pad 103”) opposite to the first end in a first direction;
a solder (“solder bump 105”) on the first end of the conductive pillar; and
a plurality of surfaces at the second end of the conductive pillar (surfaces of “copper seed layer 106” in “micro-vias 201” formed through “passivation layer 104”, para. 0019 FIG. 1-3) in contact with the metal pad in a plurality of respective contact areas (“copper seed layer 106” contacts “metal pad 103” through the “micro-vias 201”, para. 0020 FIG. 1 and 4-5);
Jang and Jiang teach substrates with bump interconnect structures. The bump interconnects “copper structures 112” in Chen make contact with “metal pad 103” through vias in the “passivation layer 104”. Passivation layer portions between bumps and bond pads are used for absorbing stress during bonding and avoiding cracks, as shown in para. 0060 FIG. 7A-7G of Choi’512 and para. 0050 FIG. 1-3 of Shin. Furthermore, the vias through the passivation layer may be smaller than a probe needle width, such that the probe needle will not contact the underlying pad as taught in para. 0041-0044 of Sawai. In this manner, correct testing for defective or missing bumps is achieved instead of mistaking electrical contact with the pad for electrical contact with a bump. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that micro-vias through “passivation layer 104” on “metal pad 103” help reduce stress on the “copper structure 112” and to avoid false positives during wafer testing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the IC package in Jang with the conductive pillar having a plurality of contact surfaces as taught between Jiang, Choi, Shin, and Sawai. By contacting the bond bad with a plurality of contact areas instead of a single large contact area, stress on the bump interconnect is reduced. In cases where the conductive pillars of the bump interconnect are not formed due to a manufacturing problem, false positives can be avoided because a probe needle would be too big to contact the bond pad through the openings of the passivation layer.
Regarding claim 20, Jang, modified by Jiang, Choi’512, Shin, and Sawai, teach the IC package of claim 19, each bump interconnect further comprising: a passivation layer (“passivation layer 104” para. 0019) disposed between, in the first direction, a perimeter of the second end of the conductive pillar and the metal pad (a portion of “passivation layer 104” is between the perimeter of “copper structure 112” and “metal pad 103”); and
a passivation layer (“passivation layer 104”) disposed around and isolating each of the plurality of surfaces of the second end of the conductive pillar (portions of “passivation layer 104” are around the “micro-vias 201”, FIG. 1-2).
Regarding claim 21, Jang, modified by Jiang, Choi’512, Shin, and Sawai, teach the IC package of claim 19, wherein, in each bump interconnect: the passivation layer comprises openings (“micro-vias 201” as seen in FIG. 2) corresponding to each of the plurality of contact areas; and
the second end of the conductive pillar extends through the openings to form the plurality of contact areas of the conductive pillar in contact with the metal pad (“copper seed layer 106” and lower portion of “copper structure 112” extend through the micro-vias to contact “metal pad 103”, para. 0015).
Regarding claim 22, Jang, modified by Jiang, Choi’512, Shin, and Sawai, teach the IC of claim 19, wherein: the plurality of surfaces comprises a uniform pattern of end surfaces of the second end of the conductive pillar (the plurality of surfaces of “copper seed layer 106” through the vias appear substantially uniform in Jiang FIG. 1).
Regarding claim 24, Jang, modified by Jiang, Choi’512, Shin, and Sawai, teach the IC package of claim 19, wherein: the plurality of contact areas comprises at least four (4) contact areas (FIG. 1 shows six surfaces of “copper seed layer 106” in contact with “metal pad 103”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang, modified by Choi, as applied to claim 2 above, in view of Lin et al. US 20120032322 A1 (hereinafter referred to as Lin).
Jiang, modified by Choi, teach the IC of claim 2, the passivation layer further comprising: a hard passivation layer (“passivation layer 104” comprises silicon nitride, para. 0015).
However, Jiang, modified by Choi, fail to teach a polymer passivation layer (320) and the hard passivation layer (318) disposed between, in the first direction, the polymer passivation layer and the metal pad.
Nevertheless, Lin teaches
a polymer passivation layer (“stress buffering layer 326” made of polyimide, polybenzoxazole, or a combination thereof, para. 0029 FIG. 5) and
the hard passivation layer (“second passivation layer 324” para. 0029) disposed between, in the first direction, the polymer passivation layer and the metal pad (“second passivation layer 324” is between “stress buffering layer 326” and “topmost metal layer 323”, para. 0029 FIG. 5).
Jiang, modified by Choi, and Lin teach passivation layers with openings over bond pads. The passivation structure in Jiang only uses a single silicon nitride “passivation layer 104” while the structure in Lin comprises a silicon nitride “second passivation layer 324” covered by a polymer “stress buffering layer 326”. Polyimide has a Young’s modulus around 2.76 GPa as shown in Dupont Kapton Polyimide Film General Specifications while silicon nitride has a Young’s modulus around 310 GPa as seen in Silicon Nitride, Si3N4 Ceramic Properties by Accuratus. From this, it is understood that polyimide “stress buffering layer 326” can handle greater stress and compression than a single layer of silicon nitride. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the passivation layer in Lin can better reduce the stress due to the use of polyimide “stress buffering layer 326” over the silicon nitride “second passivation layer 324”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the passivation layer taught between Jiang and Choi with the passivation layer taught in Lin. A passivation layer including a polymer passivation layer can reduce more stress than a hard passivation layer alone.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang, modified by Choi, as applied to claim 1 above, in view of Yu et al. US 20180158789 A1 (hereinafter referred to as Yu), further in view of Lin et al. US 20120032322 A1 (hereinafter referred to as Lin).
Jiang, modified by Choi, teach the IC of claim 1 but fail to teach wherein: each of the plurality of surfaces comprises a circular surface area.
Nevertheless, Yu teaches
wherein: each of the plurality of surfaces comprises a circular surface area (“second openings 123” over “first redistribution layer 117” are circular and filled with “first conductive element 301”, para. 0034 and 0036 FIG. 3C).
Jiang, modified by Choi, and Yu teach conductive pillars with a plurality of surfaces in contact with a metal pad. While the surfaces of “copper seer layer 106” in Jiang may be rectangular or square (para. 0019), the surfaces in Yu are shown as circles in FIG 3C. The portions of “polymer layer 121” around the “second openings 123” are the “support structure 125” (para. 0038) analogous to how the portions of the passivation layer around the plurality of surfaces provide support in Jiang and Choi. Furthermore, Lin teaches that “openings 326b and 326c” in the “stress buffering layer 326” and “second passivation layer 324” can be any shape (Lin para. 0031 FIG. 5). In a different embodiment in Lin, “opening 312c” is shown as circular (Lin FIG. 6). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the surfaces of “copper seed layer 106” of the conductive pillar can have square, rectangular, or circular shapes so long as enough connectivity and support for the conductive pillar is achieved.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip taught between Jiang and Choi with the circular surface area taught in Yu and further taught in Lin. Any area shape, including a circular surface area, is effective in forming contact with the metal pad. The remaining passivation layer around the circular surface areas supports the conductive pillar.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Jang, modified by Jiang, Choi’512, Shin, and Sawai, as applied to claim 19 above, in view of Yu et al. US 20180158789 A1 (hereinafter referred to as Yu), and further in view of Lin et al. US 20120032322 A1 (hereinafter referred to as Lin).
Jang, modified by Jiang, Choi’512, Shin, and Sawai, teach the IC of claim 19 but fail to teach wherein: each of the plurality of surfaces comprises a circular surface area.
Nevertheless, Yu teaches
wherein: each of the plurality of surfaces comprises a circular surface area (“second openings 123” over “first redistribution layer 117” are circular and filled with “first conductive element 301”, para. 0034 and 0036 FIG. 3C).
Jang, modified by Jiang, Choi’512, Shin, and Sawai, and Yu teach conductive pillars with a plurality of surfaces in contact with a metal pad. While the surfaces of “copper seer layer 106” in Jiang may be rectangular or square (para. 0019), the surfaces in Yu are shown as circles in FIG 3C. The portions of “polymer layer 121” around the “second openings 123” are the “support structure 125” (para. 0038) analogous to how the portions of the passivation layer around the plurality of surfaces provide support in Jiang and Choi. Furthermore, Lin teaches that “openings 326b and 326c” in the “stress buffering layer 326” and “second passivation layer 324” can be any shape (Lin para. 0031 FIG. 5). In a different embodiment in Lin, “opening 312c” is shown as circular (Lin FIG. 6). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the surfaces of “copper seed layer 106” of the conductive pillar can have square, rectangular, or circular shapes so long as enough connectivity and support for the conductive pillar is achieved.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the IC chip taught between Jiang and Choi with the circular surface area taught in Yu and further taught in Lin. Any area shape, including a circular surface area, is effective in forming contact with the metal pad. The remaining passivation layer around the circular surface areas supports the conductive pillar.
Allowable Subject Matter
Claims 11, 17-18, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the most relevant prior art Yu et al. US 20180158789 A1 teaches that any number of openings can be made in the passivation layer as long as connectivity and structural support are maintained (para. 0036). Though this implies that 10 or even more openings can be made, there is no obvious reason to do so. Therefore, claim 11 is considered to contain allowable subject matter.
Regarding claim 17, the most relevant prior art Lin et al. US 20120032322 A1 teaches a polymer passivation layer formed on the hard passivation layer. However, Lin fails to teach: forming a second passivation mask on the first side of the first substrate, the polymer passivation layer comprising openings to the metal pad based on the second passivation mask. Therefore, claim 17 is considered to contain allowable subject matter.
Regarding claim 18, it is objected to based on its dependence on claim 18.
Regarding claim 25, it is considered to contain allowable subject matter for the same reasons as claim 11.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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