The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant’s election of the embodiment of figure 4 in the reply filed on 12/8/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7 and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (9,876,118).
Regarding claim 1, Yamazaki et al. teach in figure 1C and related text a semiconductor device comprising a transistor, the transistor comprising:
a gate line a part of which functions as a first gate electrode 13;
a first gate insulating film 15 over the first gate electrode;
at least one semiconductor film 17 located over the first gate insulating film and overlapping the first gate electrode 13;
a pair of terminals (the vertical elements of element 31) over and electrically connected to the at least one semiconductor film;
a second gate insulating film 28 over the pair of terminals; and
a second gate electrode 13 having an electrical field shielding property, located over the second gate insulating film, overlapping the first gate electrode and the at least one semiconductor film, and electrically connected to the first gate electrode through a first pair of openings 42, 43 formed in the first gate insulating film 15 and the second gate insulating film 28,
wherein the first pair of openings sandwich the at least one semiconductor film 17 in one of a channel width direction and a channel length direction of the transistor,
a length of the first pair of openings in the channel width direction is larger than a channel width of the transistor when the first pair of openings sandwich the at least one semiconductor film in the channel length direction (see figure 1A), and
a length of the first pair of openings in the channel length direction is larger than a channel length of the transistor when the first pair of openings sandwich the at least one semiconductor film in the channel width direction (see figure 1A).
Yamazaki et al. do not explicitly state that the second gate electrode is having a light shielding property.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second gate electrode having a light shielding property, in Yamazaki et al.’s device, in order to improve the device characteristics.
Regarding claim 2, Yamazaki et al. teach in figure 1C and related text that the first pair of openings sandwich the pair of terminals (the inner walls of the terminals) in the channel length direction or the channel width direction.
Regarding claim 4, Yamazaki et al. teach in figures 1A, 1C and related text that a length of the second pair of openings in the channel width direction is larger than the channel width of the transistor when the second pair of openings sandwich the at least one semiconductor film in the channel length direction, and a length of the second pair of openings in the channel length direction is larger than the channel length of the transistor when the second pair of openings sandwich the at least one semiconductor film in the channel width direction.
Regarding claim 7, Yamazaki et al. teach in figure 23A and related text a signal line 109 over the first gate insulating film (since the signal line is part of one of the terminals), wherein one of the pair of terminals is a part of the signal line, is branched from the signal line, and is arranged parallel to the gate line (see figure 1C).
Regarding claim 10, Yamazaki et al. teach in figure 30A and related text a substrate under the transistor 901; a counter substrate 906 over the transistor; and a light source exposed from the counter substrate (inherently therein in order for the device to operate) in a normal direction of the substrate.
Regarding claim 11, Yamazaki et al. do not teach that the light source comprises a plurality of light-emitting elements arranged in a direction parallel to an extending direction of the gate line. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a plurality of light-emitting elements arranged in a direction parallel to an extending direction of the gate line in Yamazaki et al.’s device, in order to operate the device in its intended use and in order to simplify the processing steps of making the device.
Regarding claim 12, Yamazaki et al. teach in figure 30A and related text a housing accommodating a part of the substrate, a part of the counter substrate, and the light source.
Regarding claim 13, Yamazaki et al. teach in figure 30A and related text a bottom surface of the substrate 901 and an upper surface of the counter substrate 906 are exposed from the housing.
Regarding claim 14, Yamazaki et al. teach in figure 23B and related text a liquid crystal element 121 electrically connected to one of the pair of terminals.
Regarding claim 15, Yamazaki et al. teach in figure 1C and related text that the at least one semiconductor film includes an oxide semiconductor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
2/5/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800