DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Package substrate having through-hole structures for improved power performance and method of forming the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheah et al. (U.S. Pub. 2020/0168559).
In re claim 1, Cheah discloses a package substrate 400 comprising surface layers (430,432,434) with a power region for coupling with a semiconductor device 462 (see paragraph [0055] and fig. 4); base layers 458 (see paragraph [0056] and fig. 4); a core layer 410 with a top surface and a bottom surface (see paragraph [0056] and fig. 4), wherein the core layer 410 is disposed between the surface layers (430,432,434) and the base layers 458 (see paragraphs [0055], [0056] and fig. 4); and a plurality of through hole vias (420,422,424,426) providing direct couplings between the surface layers (430,432,434) with the base layers 458 (see paragraph [0054] and fig. 4), wherein the plurality of through hole vias (420,422,424,426) are located in the power region below the semiconductor device 462 positioned over the surface layers (430,432,434) (see paragraphs [0054], [0055] and fig. 4).
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In re claim 2, as applied to claim 1 above, Cheah discloses wherein the surface layers (430,432,434) comprise a first plurality of micro vias (vias located inside the surface layers (430,432,434)) coupling the surface layers to each other (see paragraph [0055] and fig. 4).
In re claim 3, as applied to claim 1 above, Cheah discloses wherein the base layers 458 comprise a second plurality of micro vias (vias located in the base layers 458) coupling the base layers to each other (see paragraph [0056] and fig. 4).
In re claim 4, as applied to claim 1 above, Cheah discloses wherein the through hole vias 426 extend through the top surface of the core layer 410 to the surface layers (430,432,434) and extend below the bottom surface of the core layer 410 to the base layers 458 (see paragraphs [0055], [0056] and fig. 4).
In re claim 5, as applied to claim 4 above, Cheah discloses wherein the package substrate further comprises a first plurality of plane layers (upper 414) positioned between the top surface of the core layer 410 and the surface layers (430,432,434) (see paragraph [0053] and fig. 4).
In re claim 6, as applied to claim 5 above, Cheah discloses wherein the first plurality of plane layers (upper 414) is without micro vias (see paragraph [0053] and fig. 4).
In re claim 7, as applied to claim 4 above, Cheah discloses wherein the package substrate further comprises a second plurality of plane layers (lower 414) positioned between the bottom surface of the core layer 410 and the base layers 458 (see paragraph [0053] and fig. 4).
In re claim 8, as applied to claim 7 above, Cheah discloses wherein the second plurality of plane layers (lower 414) are without micro vias (see paragraph [0053] and fig. 4).
In re claim 9, as applied to claim 5 above, Cheah discloses wherein the through hole vias (420,422,424,426) couple one or more of the first plurality of plane layers (upper 414) with the surface layers (430,432,434) (see paragraphs [0053], [0056] and fig. 4).
In re claim 10, as applied to claim 7 above, Cheah discloses wherein the through hole vias (420,422,424,426) couple one or more of the second plurality of plane layers (lower 424) with the base layers 458 (see paragraphs [0053, [0054], [0056] and fig. 4).
In re claim 11, as applied to claim 1 above, Cheah discloses wherein one or more of the through hole vias 426 provide a power coupling between the surface layers (430,432,434) and the base layers 458 (see paragraph [0054] and fig. 4).
In re claim 12, as applied to claim 1 above, Cheah discloses wherein one or more of the through hole vias 420 provide a ground coupling between the surface layers (430,432,434) and the base layers 458 (see paragraph [0054] and fig. 4).
In re claim 13, Cheah discloses a method comprising providing a core layer 410 for a package substrate 400, wherein the core layer 410 has a top surface and a bottom surface (see paragraph [0055] and fig. 4); forming a first plurality of plane layers (upper 414) on the top surface of the core layer 410 (see paragraph [0053] and fig. 4); forming a second plurality of plane layers (lower 414) on the bottom surface of the core layer 410 (see paragraph [0053] and fig. 4); forming a plurality of through vias (420, 422, 424, 426) through the first plurality of plane layers (upper 414), the core layer 410, and the second plurality of plane layers (lower 414), wherein the first and second plurality of plane layers are formed without micro vias (see paragraphs [0053], [0054] and fig. 4); forming surface layers (430, 432, 434) on the first plurality of plane layers; forming a first plurality of micro vias (vias located in the surface layers (430, 432, 434)) n the surface layers; forming base layers 458 on the second plurality of plane layers; and forming a second plurality of micro vias (vias located in the base layers 458) in the base layers (see paragraph [0055] and fig. 4).
In re claim 14, as applied to claim 13 above, Cheah discloses wherein the plurality of through hole vias (420,422,424,426) electrically couples the surface layers (430, 432, 434) to the base layers 458 (see paragraphs [0054], [0055] and fig. 4).
In re claim 15, as applied to claim 13 above, Cheah discloses wherein the method further comprises coupling a semiconductor device 462 to the surface layers (430, 432, 434), wherein the plurality of through vias (420, 422, 424, 426) provides power and ground couplings for the semiconductor device 462 coupled to the surface layers (430, 432, 434) (see paragraphs [0054], [0057] and fig. 4).
In re claim 16, Cheah discloses an electronic component 400 comprising a semiconductor device 462 (see paragraph [0057] and fig. 4); a package substrate 401 comprising surface layers (430, 432, 434) with a first plurality of micro vias (vias located in the surface layers (430, 432, 434)) for coupling with each other and to the semiconductor device 462 (see paragraphs [0056], [0057] and fig. 4), wherein the semiconductor device 462 is positioned over the surface layers (430, 432, 434) (see paragraphs [0056], [0057] and fig. 4); a core layer 410 (see paragraph [0055] and fig. 4); base layers 458 with a second plurality of micro vias (vias located in the base layers 458)) for coupling with each other (see paragraph [0056] and fig. 4); a first plurality of plane layers (upper 414) without micro vias positioned between the surface layers (430, 432, 434) and the core layer 410 (see paragraphs [0053], [0055] and fig. 4); a second plurality of plane layers (lower 414) without micro vias positioned between the core layer 410 and the base layers 458 (see paragraphs [0053], [0055] and fig. 4); and a plurality of through hole vias (420, 422, 424, 426) located below the semiconductor device 462 that passes through the first and second plurality of plane layers and the core layer 410 and couples the surface layers (430, 432, 434) with the base layers 458 (see paragraphs [0054], [0055] and fig. 4).
In re claim 17, as applied to claim 16 above, Cheah discloses wherein the through hole vias (420, 422, 424, 426) couple one or more of the first plurality of plane layers (upper 414) with the surface layers 458 (see paragraphs [0054], [0055] and fig. 4).
In re claim 18, as applied to claim 16 above, Cheah discloses wherein the through hole vias (420, 422, 424, 426) couple one or more of the second plurality of plane layers (lower 414) with the base layers 458 (see paragraphs [0053], [0056] and fig. 4).
In re claim 19, as applied to claim 16 above, Cheah discloses wherein one or more of the through hole vias 426 provide power couplings between the semiconductor device 462 and the base layers (430, 432, 434) (see paragraphs [0054], [0057] and fig. 4).
In re claim 20, as applied to claim 16 above, Cheah discloses wherein one or more of the through hole vias 420 provide ground couplings between the semiconductor device 462 and the base layers 458 (see paragraphs [0054], [0057] and fig. 4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ong et al. (U.S. Pub. 2018/0366423) discloses a package substrate comprising a surface layer (upper 401) with a power region for coupling with a semiconductor device 1002 (see paragraph [0035] and fig. 10); base layer (lower 401); a core layer 308 with a top surface and a bottom surface (see paragraph [0029] and fig. 10), wherein the core layer 308 is disposed between the surface layer and the base layer; and a plurality of through hole vias 406 providing direct couplings between the surface layer with the base layer (see paragraph [0029] and fig. 4).
Ko (U.S. Pub. 2011/0088937) discloses a package substrate comprising surface layers 105 (see paragraph [0055] and fig. 32); base layers 112 (see paragraph [0055] and fig. 32); a core layer 101 with a top surface and a bottom surface, wherein the core layer 101 is disposed between the surface layers 105 and the base layers 112 (see paragraph [0057] and fig. 32); and a plurality of through hole vias 102 providing direct couplings between the surface layers 105 with the base layers 112 (see paragraph [0058] and fig. 32).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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