Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/14/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 19-20, 23, and 33-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rios (US 20200066326 A1).
Regarding claim 1, Rios discloses a memory device (Fig. 8), comprising:
a first connection line layer (RWL), a second connection line layer (RBL), a third connection line layer (Gnd), and a fourth connection line layer (WBL-A, See annotated figure) that are sequentially disposed (Note: the lines are at a plurality of vertical heights. This necessarily requires sequentially disposition, rather than simultaneous disposition) in a vertical direction (See annotated figure for direction designation) with respect to a substrate (See annotated figure), wherein the first connection line layer comprises a plurality of first conductive lines (See additional remarks below regarding “plurality”) extending parallel to each other in a first direction (into the page; [0048]: “may extend into and out of the plane of the page to connect with other TFTs”), one of the second connection line layer and the third connection line layer comprises a plurality of conductive lines (See remarks below regarding “plurality”) extending parallel to each other in a second direction intersecting the first direction (There is at least some dimension shown in the 2nd direction, thus each extends in the 2nd direction. See annotated figure for direction designation.), and the fourth connection line layer comprises a plurality of fourth conductive lines (See additional remarks below regarding “plurality”) extending parallel to each other in a third direction (into the page; [0048]: “may extend into and out of the plane of the page to connect with other TFTs”);
a plurality of memory cells ([0014]: “a 3T memory cell”); “plurality” is taught by [0048]: “array” which is defined as a plurality of memory cells in [0040]: “array…of memory cells”), wherein each memory cell extends vertically from a corresponding first conductive line in the first connection line layer (the memory cell of Fig. 8 extends vertically above line layer RWL) and respectively forms electrical connections with the second connection line layer or a corresponding conductive line in the second connection line layer (the memory cell of Fig. 8 includes an electrical connection with RBL), the third connection line layer or a corresponding conductive line in the third connection line layer (the memory cell of Fig. 8 includes an electrical connection with Gnd), and a corresponding fourth conductive line in the fourth connection line layer (the memory cell of Fig. 8 includes an electrical connection with WBL-A), and each memory cell comprises a first transistor (T3), a second transistor (T2), and a third transistor (T1) that are stacked on each other in the vertical direction,
wherein the first transistor comprises:
a first active layer, comprising a first source/drain region (SD1-1) electrically connected with the second connection line layer or the corresponding conductive line in the second connection line layer (SD1-1 is electrically connected to RBL), a second source/drain region (SD1-2), and a channel region (CH1) between the first source/drain region of the first transistor and the second source/drain region of the first transistor in the vertical direction (a portion of the channel has a vertical elevation between an elevation of portions of the first and second source/drain regions; See dashed elevation reference lines);
a first gate dielectric layer on the first active layer (GD1); and
a first gate conductor layer (GC1, the portion of RWL corresponding to the single illustrated cell) on the first gate dielectric layer, wherein the first gate conductor layer extends towards the corresponding first conductive line in the first connection line layer (GC1 is a portion of RWL thus it extends towards RWL) to be electrically connected to the corresponding first conductive line in the first connection line layer (GC1 is a portion of RWL thus it is electrically connected to RWL),
wherein the second transistor comprises:
a second active layer, comprising a first source/drain region (SD2-1), a second source/drain region (SD2-2) electrically connected with the third connection line layer or the corresponding conductive line in the third connection line layer (SD2-2 is electrically connected to Gnd), and a channel region (CH2) between the first source/drain region of the second transistor and the second source/drain region of the second transistor in the vertical direction (a portion of the channel has a vertical elevation between an elevation of portions of the first and second source/drain regions; See dashed elevation reference lines), wherein the second source/drain region of the first transistor and the first source/drain region of the second transistor are close to each other (each are within the same memory cell, and therefore “close”) and electrically connected with each other (SD1-2 and SD2-1 are directly electrically connected);
a second gate dielectric layer (GD2) on the second active layer; and
a second gate conductor layer (S) on the second gate dielectric layer, wherein the second gate conductor layer and the first gate conductor layer are electrically isolated from each other (the schematic shows electrical isolation between S and RWL), and
wherein the third transistor comprises:
a third active layer, comprising a first source/drain region (SD3-1) electrically connected with the second gate conductor layer (SD3-1 and S are directly electrically connected), a second source/drain region (SD3-2) electrically connected with the corresponding fourth conductive line in the fourth connection line layer (SD3-2 and WBL-A are directly electrically connected), and a channel region (CH3) between the first source/drain region of the third transistor and the second source/drain region of the third transistor in the vertical direction (a portion of the channel has a vertical elevation between an elevation of portions of the first and second source/drain regions; See dashed elevation reference lines);
a third gate dielectric layer on the third active layer (GD3); and
a third gate conductor layer (GC3, the portion of WWL corresponding to the single illustrated cell) on the third gate dielectric layer,
and a fifth connection line layer (WWL) above the memory cell, wherein the fifth connection line layer comprises a plurality of fifth conductive lines (See additional remarks below regarding “plurality”) extending in a fourth direction intersecting the third direction (There is at least some dimension shown in the 4th direction, thus each extends in the 4th direction. See annotated figure for direction designation.), and the third gate conductor layer of each memory cell is electrically connected to a corresponding fifth conductive line in the fifth connection line layer (GC3 is a portion of WWL thus it is electrically connected to WWL).
Illustrated below is a marked and annotated figure of Fig. 8 of Rios.
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Regarding “a plurality of first conductive lines extending parallel to each other in a first direction”. Fig. 8 illustrates a single memory cell with a singular first conductive line ([0014]: “a 3T memory cell”). Plurality is taught by [0048]: “array” which is defined as a plurality of memory cells ([0040]: “array…of memory cells”). Fig. 4 teaches arrays are formed by pluralizing memory cells in parallel. Thus, the lines extend in the first direction and are parallel.
Regarding “a plurality of conductive lines extending parallel to each other in a second direction intersecting the first direction”. Fig. 8 illustrates a single memory cell with singular second and third conductive lines ([0014]: “a 3T memory cell”). Plurality is taught by [0048]: “array” which is defined as a plurality of memory cells ([0040]: “array…of memory cells”). Fig. 4 teaches arrays are formed by pluralizing memory cells in parallel. Thus, the lines extend in the second direction and are parallel.
Regarding “a plurality of fourth conductive lines extending parallel to each other in a third direction”. Fig. 8 illustrates a single memory cell with a singular fourth conductive line ([0014]: “a 3T memory cell”). Plurality is taught by [0048]: “array” which is defined as a plurality of memory cells ([0040]: “array…of memory cells”). Fig. 4 teaches arrays are formed by pluralizing memory cells in parallel. Thus, the lines extend in the third direction and are parallel.
Regarding “a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction”. Fig. 8 illustrates a single memory cell with singular fifth conductive line ([0014]: “a 3T memory cell”). Plurality is taught by [0048]: “array” which is defined as a plurality of memory cells ([0040]: “array…of memory cells”). Fig. 4 teaches arrays are formed by pluralizing memory cells in parallel. Thus, the lines extend in the fourth direction and are parallel.
Regarding claim 2, Rios discloses the memory device according to claim 1 (Fig. 8), wherein portions where the first active layer, the second active layer and the third active layer are adjacent to each other are substantially aligned in the vertical direction (See dashed reference line).
Illustrated below is a marked and annotated figure of Fig. 8 of Rios.
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Regarding claim 3, Rios discloses the memory device according to claim 2 (Fig. 8), wherein portions where an outer sidewall of the first active layer, an outer sidewall of the second active layer and an outer sidewall of the third active layer are adjacent to each other are substantially coplanar in the vertical direction (See dashed reference line).
Regarding claim 4, Rios discloses the memory device according to claim 1 (Fig. 8), wherein each memory cell is surrounded by at least one of the second connection line layer or the corresponding conductive line in the second connection line layer, the third connection line layer or the corresponding conductive line in the third connection line layer, and the corresponding fourth conductive line in the fourth connection line layer (the storage node S of the memory cell has the 2nd/3rd/4th layers RBL/Gnd/WBL-A on various sides, thus “surrounded by”).
Regarding claim 5, Rios discloses the memory device according to claim 1 (Fig. 8), wherein the other of the second connection line layer and the third connection line layer is an integrated conductive plate ([0045]: “pinned to ground”).
Regarding claim 19, Rios discloses the memory device according to claim 1 (Fig. 8), wherein at least one of the first active layer, the second active layer, and the third active layer comprises indium gallium zinc oxide ([0046]: “The TFT may be formed of …IGZO”).
Regarding claim 20, Rios discloses the memory device according to claim 1 (Fig. 8), wherein the second active layer comprises a semiconductor material ([0046]: “The TFT may be formed of …IGZO”) with a relatively high mobility (high relative to dielectric materials), and the third active layer comprises a semiconductor material ([0046]: “The TFT may be formed of …IGZO”) with a relatively low leakage ([0027]: “An IGZO…is able to provide an ultra-low off state leakage current”) or a relatively large bandgap width.
Regarding claim 23, Rios discloses the memory device according to claim 1 (Fig. 8), wherein the memory device is a dynamic random access memory (Rios describes the embodiments as improvements to traditional DRAM by substituting the capacitor, with transistor circuitry; [0020]: “The charged sensing transistor provides two important advantages over a storage capacitor”. Therefore, the disclosed embodiments are an improved DRAM), the first conductive line corresponds to a read word line ([0044]: “read word line”), the corresponding conductive line of one of the second connection line layer and the third connection line layer corresponds to a read bit line ([0044]: “read bit line”), the corresponding conductive line of the other of the second connection line layer and the third connection line layer corresponds to a ground plane ([0045]: “pinned to ground”), the fourth conductive line corresponds to a write bit line ([0044]: “write bit line”), and the fifth conductive line corresponds to a write word line ([0044]: “write word line”).
Regarding claim 33, Rios discloses an electronic apparatus, comprising the memory device according to claim 1 ([0061]: “the integrated circuit die of the processor, memory devices, communication devices, or other components are fabricated to include vertical memory elements or memory elements with low leakage transistors as described herein”).
Regarding claim 34, Rios discloses the electronic apparatus according to claim 33, wherein the electronic apparatus comprises a smart phone ([0062]: “a smart phone”), a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.
Allowable Subject Matter
Claims 6-18 and 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 6-18 is the inclusion of the limitation “wherein the first active layer and the second active layer are provided by a same semiconductor layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first active layer”, “second active layer”, and “same semiconductor layer” in combination with all other limitations in claim 6 because these layers are separate and distinct structurally and materially.
The primary reason for the allowable subject matter of claims 21-22 is the inclusion of the limitation “wherein the first active layer, the second active layer, and the third active layer are self-aligned in the vertical direction” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first active layer”, “second active layer”, “third active layer”, and “self aligned” in combination with all other limitations in claim 21 because the prior art does not teach a self aligned process, and because the product made does have a configuration that would reasonably suggest using a self aligned process.
Response to Arguments
Applicant's arguments filed 3/12/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to claim 1 that “the positional relationship between RWL and RBL is different from the positional relationship between the first connection line layer and the second connection line layer. Therefore, Rios’ RWL cannot be equivalent to the “first connection line layer” of claim 1, and Rios’ RBL cannot be equivalent to the “second connection line layer” of claim 1”. Remarks at pg. 16.
Examiner’s reply:
The examiner disagrees and firstly points to MPEP 2111: Broadest Reasonable Interpretation as it is applied to “layer” in the interpretation of the prior art. The examiner does not find “layer” as written precluding mapping of the two contended separate and distinct structures as two separate and distinct layers. Additionally, the examiner points to Rios: Fig. 8 which shows the contended RWL and RBL layers having at least some surfaces existing at different vertical positions (See the surfaces nearest the substrate), thus these two separate and distinct layers that exist at different heights may reasonably be interpreted as different layers.
Secondly, In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the positional relationship”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The rejection is maintained for the same reasons as before.
Applicant argues:
Applicant argues with respect to claim 1 that “those skilled in the art have no motivation to obtain the active layer structure defined by claim 1 from Rios’ FIG. 8. In fact, Rios' entire article does not involve the specific structure of the active layer in transistors. On page 8 of this OA, the dashed lines marked in T3 of FIG. 8 of Rios is not the actual content disclosed by Rios, but rather the result of the examiner subjectively equating Rios with this application after reading this application”. Remarks at pg. 17.
Examiner’s reply:
The examiner does not find Applicant’s arguments persuasive because the claim as written reasonably includes a plurality of transistor structural configurations beyond those expressly disclosed by Applicant. The examiner has not relied an imported/recreated interpretation beyond the disclosure of Rios, but rather has provided annotated reference lines indicating the portions of the generic regions relied upon to meet the claim (i.e., which portion of an otherwise generic, ordinary and customary source/drain/channel region), consistent with MPEP 2111. The examiner finds the claim as written broad enough to encompass portions of regions, and these portions happen to be at different heights. Although the examiner believes Applicant is attempting to assert and describe differences between the disclosure and the prior art, the claim as written reasonably encompasses configurations beyond the disclosure. The rejection is maintained for the same reasons as before.
Applicant argues:
Applicant argues with respect to claim 1 that “Although Rios mentioned that the transistor includes a gate, it did not specify the specific structure of the gate, let alone the “positional relationship between the gate dielectric layer and the gate conductor layer” or the “electrical connection between the gate conductor layer and the connection line layer”. In addition, FIG. 8 of Rios does not show any gates, and thus those skilled in the art have no motivation to obtain the gate structure defined by claim 1 from FIG. 8 of Rios”. Remarks at pg. 18.
Examiner’s reply:
The examiner does not find Applicant’s arguments persuasive because the claim as written reasonably includes a plurality of transistor structural configurations beyond those expressly disclosed by Applicant. The examiner has not relied an imported/recreated interpretation beyond the disclosure of Rios, but rather has relied upon the reference to teach a gate and dielectric configuration within the breadth of the claim as written, consistent with MPEP 2111. The examiner finds the claim as written broad enough to encompass generic gates and dielectrics, and finds Rios teaching these generic gates and dielectrics. Although the examiner believes Applicant is attempting to assert and describe differences between the disclosure and the prior art, the claim as written reasonably encompasses configurations beyond the disclosure. The rejection is maintained for the same reasons as before.
Applicant argues:
Applicant argues with respect to claim 1 that “there is a contradiction in the equivalence of the examiner. Specifically, when evaluating claim 1, the examiner equated Rios' RWL with both the "first connection line layer" and the "first gate conductor layer" of claim 1; Also, the examiner equated Rios' WWL with both the "fifth connection line layer" and the "third gate conductor layer" of claim 1. That is to say, the examiner equated the same structure of Rios with two different structures of claim 1, which is obviously illogical”. Remarks at pg. 19.
Examiner’s reply:
The examiner disagrees and firstly points to MPEP 2111: Broadest Reasonable Interpretation as it is applied to “layer” in the interpretation of the prior art. The examiner does not find “layer” as written precluding mapping of the two contended separate and distinct structures as two separate and distinct layers. Additionally, the examiner points to Rios: Fig. 8 which shows the contended RWL/RBL and WWL/WBL layers having at least some surfaces existing at different vertical positions (See the surfaces nearest the substrate), thus these two separate and distinct layers that exist at different heights may reasonably be interpreted as different layers. The rejection is maintained for the same reasons as before.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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