Prosecution Insights
Last updated: April 18, 2026
Application No. 18/318,993

CONTACT STRUCTURE AND A GATE LINE SLIT AND MERGE METHOD TO FORM THEREOF

Non-Final OA §102§103§112
Filed
May 17, 2023
Examiner
GREWAL, HEIM KIRIN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
93%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
23 granted / 25 resolved
+24.0% vs TC avg
Minimal +1% lift
Without
With
+0.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
29 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
54.1%
+14.1% vs TC avg
§102
29.4%
-10.6% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 25 resolved cases

Office Action

§102 §103 §112
CTNF 18/318,993 CTNF 99861 Detailed Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims The following is in response to the communication filed 1/20/2026. Claims 1-20 are currently pending. Claims 1-14 have been withdrawn. Claims 15-20 have been examined. Priority Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to China patent application No. 2023104474881, filed on April 23, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Furthermore, the applicant' s claim for benefit of Provisional Patent Application Serial No. 63/433,284, filed on December 16, 2022 has been received and acknowledged. Election/Restriction Applicant’s election without traverse of Group II, Claims 15-20, in the reply filed on 1/20/2026 is acknowledged. Claims 1-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group I, there being no allowable generic or linking claim. Drawings REFERENCE NUMBERS NOT IN THE SPECIFICATION 06-22-07 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 331(a)-(c) and 332(a)-(c) . Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: The description of Fig. 3B does not include any mention of reference number 331(a)-(c) or 332(a)-(c) which are included in the drawing. Appropriate correction is required. Applicant is reminded that 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. First, the term “threshold” in claim 19 is a relative term which renders the claim indefinite. The term “threshold” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. From the claim alone it is not clear if the threshold is a range of values or a single value. If the term is a range of values, the specification supports a given a range of values from 0.5 and 1.5 or 0.5 and 0.9 (Specification, [0120]), however the limitations of the specification are not read into the limitation. Even when read within the light of the specification, there is no support within the specification that that size threshold value is less than 0.5. Second, where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp. , 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “critical dimension” in claim 19 is used by the claim to mean “or a smallest possible feature size in lithography,” (Specification, [0069].) but directly following that the minimum feature size of the gate line slit (in the range of nanometers) and the contact structure (in the range of micrometers) respectively are cited. (Specification, [0069].) The smallest possible feature size that capable for manufacturing would be a single value dictated by the manufacturing process. The minimum feature size may be, and in many cases is, larger than the critical dimension. Therefore the term is indefinite because the specification does not clearly redefine the term. For purposes of examination either “a smallest possible feature size in lithography” or “a minimum feature size” will be read for the term “critical dimension.” For the purpose of examination claim 19 will be read as “wherein a ratio between a critical dimension of each of the plurality of contact structures and a critical dimension of each of the plurality of gate line trenches is less than or equal to a threshold value .” Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 15-18 and 20 is/are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Tanaka et al. US 20220005824 A1 (hereinafter Tanaka) . Regarding claim 15, Tanaka discloses: A semiconductor device, (Tanaka, at least Fig. 30 showing the first embodiment.) comprising: a substrate; (substrate 8) a stack of alternative layers including insulating layers (insulating layers 132) and gate layers (conductive layers 146) that are stacked alternatively over the substrate, (See Fig. 25) the stack of alternative layers including an array region (array region 100) and a contact region; (contact region 200) a plurality of channel structures (Fig. 30 the memory opening fill structures 58) disposed through the stack of alternative layers in the array region, (See close up in Fig. 22.) each channel structure forming a stack of transistors in a series configuration with the gate layers being gate terminals of the stack of transistors; a plurality of contact structures disposed in the contact region, (via fill 86 disposed in contact region 200) each contact structure electrically connecting to one of the gate layers; and a plurality of gate line trenches (backside trench 79) disposed through the stack of alternative layers in the array region and in the contact region, the gate line trenches being formed during the formation of the plurality of contact structures in the contact region. (See Fig. 30.) Regarding claim 16, Tanaka further discloses: one or more sacrificial layers (Fig.25 includes source-level material layers 110 which Fig. 1C magnifies to shows that the source-level material layer includes a lower sacrificial liner 103.) that underneath the plurality of contact structures. (See Fig. 25, source-level material layers 110 is below the contact via fill 86.) Regarding claim 17, Tanaka further discloses: wherein each of the plurality of contact structures includes a first spacer layer on a sidewall of the respective contact structure. (See close up in Fig. 30, dielectric spacer 84 is on the sidewall of the vial fill 86.) Regarding claim 18, Tanaka further discloses: wherein each of the plurality of gate line trenches ( backside trench 79) includes a second spacer layer on a sidewall of the respective gate line trench. (Close up shown in Fig. 22D, drain-select-level isolation structures 72) Regarding claim 20 , Tanaka discloses: A memory system, (Tanaka, [0076], monolithic three-dimensional memory array) comprising: one or more memory devices ([0076], monolithic three-dimensional memory array having an array implies that there more than one memory device.) and a memory controller that is coupled to and controls the one or more memory devices, ([0076], driver circuits for the memory device.) wherein each of the one or more memory devices comprises a substrate; (substrate 8) a stack of alternative layers including insulating layers (insulating layers 132) and gate layers (conductive layers 146) that are stacked alternatively over the substrate, (See Fig. 25) the stack of alternative layers including an array region (array region 100) and a contact region; (contact region 200) a plurality of channel structures (Fig. 30 the memory opening fill structures 58) disposed through the stack of alternative layers in the array region, (See close up in Fig. 22.) each channel structure forming a stack of transistors in a series configuration with the gate layers being gate terminals of the stack of transistors; a plurality of contact structures disposed in the contact region, (via fill 86 disposed in contact region 200) each contact structure electrically connecting to one of the gate layers; and a plurality of gate line trenches (backside trench 79) disposed through the stack of alternative layers in the array region and in the contact region, the gate line trenches being formed during the formation of the plurality of contact structures in the contact region. (See Fig. 30.) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka . Regarding claim 19, Tanaka discloses all the elements of claim 15. Tanaka does not appear to specifically disclose, “wherein a ratio between a critical dimension of each of the plurality of contact structures and a critical dimension of each of the plurality of gate line trenches is less than or equal to a threshold.” Tanaka does show in Fig. 30 that there is a minimum width (i.e. critical dimension) of the channel structures (Fig. 30 the memory opening fill structures 58) and a minimum width (i.e. critical dimension) gate line trenches (backside trench 79) , which would result in size threshold value being the ratio of those smallest feature size of the channel structure and gate line trench. The ordinary artisan would have recognized the ratio of the minimum features size to be less than or equal to a particular threshold value to be a result effective variable. Thus, it would have been obvious that the device of Tanaka would have a threshold ratio of the width of the contact structures to the smallest width of the gate line trenches, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B It is further noted that the specification contains no disclosure of either the critical nature of instant claimed range or any unexpected results arising thereof. Where patentability is said to be based upon particular chosen values or upon another variable recited in a claim, the applicant must show that the chosen values are critical. In re Woodruff, 919 F.2d 1575, 1578,16 USPQ2d 1934,1936 (Fed Cir.1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art). Prior Art Made of Record 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chun et al. US 20220052067 A1 – Figs. 21 and 22 showing an electronic system including an array memory devices . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HEIM KIRIN GREWAL/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/318,993 Page 2 Art Unit: 2812 Application/Control Number: 18/318,993 Page 3 Art Unit: 2812 Application/Control Number: 18/318,993 Page 4 Art Unit: 2812 Application/Control Number: 18/318,993 Page 5 Art Unit: 2812 Application/Control Number: 18/318,993 Page 6 Art Unit: 2812 Application/Control Number: 18/318,993 Page 7 Art Unit: 2812 Application/Control Number: 18/318,993 Page 8 Art Unit: 2812 Application/Control Number: 18/318,993 Page 9 Art Unit: 2812
Read full office action

Prosecution Timeline

May 17, 2023
Application Filed
Mar 24, 2026
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12575175
MULTIPLE GATE-ALL-AROUND SEMICONDUCTOR DEVICES WITH GATE SEPARATION
2y 5m to grant Granted Mar 10, 2026
Patent 12575206
IMAGE SENSOR, METHOD OF MANUFACTURING IMAGE SENSOR, AND ELECTRONIC DEVICE INCLUDING IMAGE SENSOR
2y 5m to grant Granted Mar 10, 2026
Patent 12568620
SEMICONDUCTOR DEVICE INCLUDING NITRIDE SPACERS
2y 5m to grant Granted Mar 03, 2026
Patent 12568683
SINGLE STACK DUAL CHANNEL GATE-ALL-AROUND NANOSHEET WITH STRAINED PFET AND BOTTOM DIELECTRIC ISOLATION NFET
2y 5m to grant Granted Mar 03, 2026
Patent 12550344
SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
93%
With Interview (+0.6%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 25 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month