Prosecution Insights
Last updated: May 29, 2026
Application No. 18/319,135

SEMICONDUCTOR PACKAGE

Non-Final OA §102§103
Filed
May 17, 2023
Priority
Sep 16, 2022 — RE 10-2022-0116884
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1509 granted / 1649 resolved
+23.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
27 currently pending
Career history
1679
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
23.7%
-16.3% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1649 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-7, 9-10, 18-19 in the reply filed on 11/12/25 is acknowledged. Claim Objections Claim 5 is objected to because of the following informalities: in line 2, “does” should be “does not”. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 5-7, and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US pub 20220013501). With respect to claim 1, Kim et al. teach a semiconductor package, comprising: (see figs. 1-4B, particularly fig. 1B and associated text): a redistribution structure 125 in which at least one redistribution layer (the lateral portion 125, third from the top) and at least one insulating layer 121, 130 are alternately stacked; a semiconductor chip 123 electrically connected to the at least one redistribution layer; and bumps 350 on the redistribution structure, wherein the redistribution structure includes: vias (the vertical parts of 125) extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes: a first UBM layer (lateral portion 125, fourth from the top) including a first metal material or an alloy of the first metal material; and a second UBM layer 150 between one of the bumps and the first UBM layer and including a second metal material different from the first metal material or an alloy of the second metal material (see para 0030), and wherein an area of a surface of the second UBM layer facing the first UBM layer is greater than an area of a surface of the first UBM layer facing the second UBM layer. With respect to claim 3, Kim et al. teach the first UBM layer contacts one of the vias, and wherein a maximum width of the first UBM layer is wider than a maximum width of one of the vias. See fig. 1B and associated text. With respect to claim 5, Kim et al. teach the second UBM layer includes a surface (edge of the second UBM layer) that does NOT overlap the first UBM layer in a vertical direction and extends around a perimeter of the first UBM layer and completely surrounds a region (middle of the second UBM layer) in which the second UBM layer overlaps the first UBM layer in the vertical direction. See fig. 1B and associated text. With respect to claim 6, Kim et al. teach the redistribution structure is between the semiconductor chip and the bumps. See fig. 1B and associated text. With respect to claim 7, Kim et al. teach an encapsulant (upper part of 121) encapsulating the semiconductor chip; and a conductive post (the vertical part right under 123) extending through the encapsulant and electrically connected to the at least one redistribution layer. See fig. 1B and associated text. With respect to claim 7, Kim et al. teach the at least one insulating layer comprises a plurality of insulating layers (parts of 121, 130 between lateral metal 125), and at least one of the plurality of insulating layers is on a side surface of the UBM structures, and wherein a surface (bottom) of the second UBM layer facing one of the bumps is on a level between an upper surface and a lower surface of the one of the plurality of insulating layers on the side surface of the UBM structures. See fig. 1B and associated text. With respect to claim 10, Kim et al. teach the at least one insulating layer is in contact with a portion of a surface (upper of edge portion of the second UBM layer) of the second UBM layer facing the first UBM layer and is in contact with a side surface of the second UBM layer. See fig. 1B and associated text. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US pub 20220013501). With respect to claim 2, Kim et al. teach the first metal material is copper but fail to teach the second metal material is nickel. However, use of nickel as UBM layer is well-known in semiconductor art. Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US pub 20220013501). With respect to claim 18, Kim et al. teach a semiconductor package, comprising: (see figs. 1-4B, particularly fig. 1B and associated text): a redistribution structure in which at least one redistribution layer 125 and at least one insulating layer 130, 121 are alternately stacked; a semiconductor chip 123 electrically connected to the at least one redistribution layer 125 ; and bumps 350 on the redistribution structure, wherein the redistribution structure includes: vias (the vertical parts of 125) extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes: a second UBM layer 150 embedded in the at least one insulating layer and including a second metal material or an alloy of the second metal material; and a first UBM layer (lateral portion 125, fourth from the top) electrically connected between one of the vias and the second UBM layer and including a first metal material different from the second metal material (see para 0030) or an alloy of the first metal material, and wherein the at least one insulating layer is in contact with a portion of a surface (upper) of the second UBM layer facing the first UBM layer and is in contact with a side surface of the second UBM layer. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US pub 20220013501). With respect to claim 19, Kim et al. teach the first metal material is copper, wherein the at least one insulating layer comprises a plurality of insulating layers(parts of 121, 130 between lateral metal 125), and one of the plurality of insulating layers is on a side surface of the UBM structures, wherein a surface (upper) of the second UBM layer facing one of the bumps is on a level between an upper surface and a lower surface of the one of the plurality of insulating layers on the side surface of the UBM structures, but fail to teach the second metal material is nickel. However, use of nickel as UBM layer is well-known in semiconductor art. Allowable Subject Matter Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having an UBM structure between an interconnect structure and a bump, the UBM structure comprises a first metal layer having a first surface area facing the second metal layer and a second metal layer having a second surface area facing the first metal layer, wherein the first and second metal layers are made of different materials and the second surface area is greater than the first surface area as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

May 17, 2023
Application Filed
Feb 23, 2026
Non-Final Rejection mailed — §102, §103
Apr 02, 2026
Examiner Interview Summary
Apr 02, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635524
ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 8m to grant Granted May 19, 2026
Patent 12635359
ARRAY SUBSTRATE AND DISPLAY PANEL
3y 5m to grant Granted May 19, 2026
Patent 12628692
SEMICONDUCTOR PACKAGE, SEMICONDUCTOR BONDING STRUCTURE, AND METHOD OF FABRICATING THE SAME
3y 5m to grant Granted May 12, 2026
Patent 12628694
INTEGRATED BARE DIE PACKAGE, AND RELATED FABRICATION METHODS
3y 4m to grant Granted May 12, 2026
Patent 12622317
PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY
4y 4m to grant Granted May 05, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1649 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month