DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The information disclosure statement (IDS) submitted on 05/17/2023 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20150115465 A1) in view of Hsu (TW 201442181 A).
Regarding claim 1, Lin discloses an integrated circuit (IC) package substrate comprising:
a first solder resist layer (212); ([0045], Fig. 3f)
a second solder resist layer (218) opposite the first solder resist layer; ([0050], Fig. 3f) and
a fiducial marker (210), ([0043], Fig. 3f)
Lin does not disclose:
including tin in an opening in the first solder resist layer.
However, Hsu discloses:
including tin (74) in an opening in the first solder resist layer (70). (Fig. 7)
From Hsu: “referring to FIG. 7, a first solder resist layer 70 is formed on the fifth conductive circuit layer 52 side, a second solder resist layer 72 is formed on the sixth conductive trace layer 62 side, and the fifth electrical layer is formed. The surface of the connection pad 524 and the sixth electrical connection pad 624 form a surface treatment layer 74”
From Hsu: “In this embodiment, the surface treatment layer 74 is formed by electroplating gold. It can be understood that the method of forming the surface treatment layer 74 may be replaced by nickel plating gold, nickel immersion gold plating, nickel plating palladium gold plating, tin plating,”)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Hsu for including tin in an opening in the first solder resist layer in order to have “high-density solder joints, thereby making the chip package substrate more versatile.” (Hsu, page 1 of translation)
Regarding claim 2, Lin discloses the IC package substrate of claim 1, further including a glass core (202) between the first and second solder resist layers (212/218). ([0041], Fig. 3f)
Regarding claim 3, Lin discloses the IC package substrate of claim 1, further including a copper pad (210) at a base of the opening (213), ([0043], Fig. 3f)
Lin does not disclose:
the pad including a surface finish, the surface finish corresponding to the tin.
However, Hsu discloses:
the pad (524) including a surface finish (74), the surface finish corresponding to the tin. (Fig. 7)
From Hsu: “ surface treatment layer 74 may be replaced by nickel plating gold, nickel immersion gold plating, nickel plating palladium gold plating, tin plating,”
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Hsu for similar reasons mentioned beforehand.
Regarding claim 4, Lin discloses the IC package substrate of claim 1, further including a metal base (210) below the opening (213), the fiducial marker (210) having an exposed surface, (Fig. 3f)
Lin does not disclose:
defined by the tin within the opening, the tin different than the metal base, the tin extending from the metal base to the exposed surface.
However, Hsu discloses:
defined by the tin (74) within the opening, the tin different than the metal base (524), the tin (74) extending from the metal base (524) to the exposed surface. (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Hsu for similar reasons mentioned beforehand.
Regarding claim 5, Lin discloses the IC package substrate of claim 1, wherein an exposed surface of the fiducial marker (210)
Lin does not disclose:
has a convex surface.
However, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to include a convex surface, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
Regarding claim 6, Lin discloses the IC package substrate of claim 1, wherein the opening (213) is one of a plurality of openings (213) in the first solder resist layer (212), (Fig. 3f)
Lin does not disclose:
the IC package substrate further including: a plurality of metal pads to electrically interconnect with a plurality of contacts on a semiconductor die; and the plurality of openings in the first solder resist layer, the plurality of openings aligned with the plurality of metal pads and filled with additional tin to electrically couple the plurality of metal pads with the plurality of contacts, the additional tin in direct contact with the plurality of metal pads.
However, Hsu discloses:
the IC package substrate further including: a plurality of metal pads (524) to electrically interconnect with a plurality of contacts (84) on a semiconductor die (82); (Fig. 8)
and the plurality of openings (see Fig. 7) in the first solder resist layer (70), the plurality of openings aligned with the plurality of metal pads (524) and filled with additional tin (74) to electrically couple the plurality of metal pads (524) with the plurality of contacts (84), the additional tin (74) in direct contact with the plurality of metal pads (524). (Fig. 7 and 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Hsu for similar reasons mentioned beforehand.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20150115465 A1) as applied to claim 1 above, and further in view of Akkinepally (US 20210090981 A1).
Regarding claim 7, Lin discloses the IC package substrate of claim 1, wherein the opening (213) is a first opening, (Fig. 3f)
Lin does not disclose
the IC package substrate further including a die-side capacitor pad in a second opening in the first solder resist layer.
However, Akkinepally discloses:
the IC package substrate (300) further including a die-side capacitor pad (340) in a second opening (338) in the first solder resist layer (336). ([0031-0032], Fig. 3C-3D)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Akkinepally for the IC package substrate further including a die-side capacitor pad in a second opening in the first solder resist layer in order to have a “ reduced size system in package components” (Akkinepally, [0002])
Regarding claim 8, Akkinepally discloses the IC package substrate of claim 7, wherein the die-side capacitor pad (340) includes a base including copper (per [0032]) and a layer (342) including tin (per [0011]), the layer on the base (340). (Fig. 3F)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Akkinepally for similar reasons mentioned beforehand.
Regarding claim 9, Akkinepally discloses the IC package substrate of claim 8, wherein the layer (342) is in contact with the base (340). (Fig. 3F)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Akkinepally for similar reasons mentioned beforehand.
Claims 10, 11, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over of Hsu (TW 201442181 A).
Regarding claim 10, Hsu discloses an integrated circuit (IC) package comprising:
a semiconductor die (82); (Fig. 8)
a package substrate (labeled 100 in Fig. 7) supporting the semiconductor die (82); and
an opening (see Fig. 7) in a surface of the package substrate (100);
a metal pad (524) at a base of the opening (see fig. 7); and
a surface finish (74) on the metal pad (524),
Hsu does not disclose:
the surface finish having a domed shape.
However, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have the surface finish having a domed shape, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
Regarding claim 11, Hsu discloses the IC package of claim 10, wherein the surface finish (74) includes tin. (From Hsu: “the surface treatment layer 74 may be replaced by…tin plating”)
Regarding claim 13, Hsu discloses the IC package of claim 10, wherein the surface finish (74) does not include a layer of nickel disposed therein. (Hsu does not mention any combination of materials for the surface finish and therefore the examiner has met the limitation)
Regarding claim 14, Hsu discloses the IC package of claim 10, wherein the package substrate (100) includes a glass core (at least (20), labeled in Fig. 4). (Fig. 7)
Regarding claim 15, Hsu discloses the IC package of claim 10, further including a plurality of bumps (84) to electrically couple the semiconductor die (82) to a corresponding plurality of contact pads (526) on the package substrate (labeled 100 in Fig. 7), the bumps (84) defined by tin in direct contact with the contact pads (526). (Fig. 7 and 8)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over of Hsu (TW 201442181 A) as applied to claim 10 above, and further in view of Tseng et al. (US 20230154861 A1).
Regarding claim 12, Hsu discloses the IC package of claim 11. Hsu does not disclose wherein the surface finish is associated with a fiducial marker, the surface finish extending from the metal pad to an exposed surface of the fiducial marker.
However, Tseng discloses:
the surface finish (64) is associated with a fiducial marker (per [0008]), the surface finish (64) extending from the metal pad (34) to an exposed surface (top) of the fiducial marker (64). (Fig. 2-3)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hsu and Tseng for the surface finish is associated with a fiducial marker, the surface finish extending from the metal pad to an exposed surface of the fiducial marker in order to “easily create a smaller see-through area and the process parameters can be easily controlled” (Tseng, abstract)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu (TW 201442181 A) as applied to claim 10 above, and further in view of Akkinepally (US 20210090981 A1).
Regarding claim 16, Hsu discloses the IC package of claim 10, wherein the surface finish (74) is a first surface finish,
Hsu does not disclose:
the IC package further including at least one of a die-side capacitor pad or a land-side capacitor pad on the package substrate, the at least one of the die-side capacitor pad or the land-side capacitor pad defined by a metal base with a second surface finish including tin in direct contact with the metal base.
However, Akkinepally discloses:
the IC package further including at least one of a die-side capacitor pad (340) or a land-side capacitor pad on the package substrate (300d), the at least one of the die-side capacitor pad (340) or the land-side capacitor pad defined by a metal base (340) with a second surface finish (372) including tin (per [0011]) in direct contact with the metal base (340). (Fig. 3F)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lin and Akkinepally for the IC package further including at least one of a die-side capacitor pad or a land-side capacitor pad on the package substrate, the at least one of the die-side capacitor pad or the land-side capacitor pad defined by a metal base with a second surface finish including tin in direct contact with the metal base in order to have a “ reduced size system in package components” (Akkinepally, [0002])
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (TW 201442181 A) in view of Lin et al. (US 20150115465 A1).
Regarding claim 17, Hsu discloses a method comprising:
providing openings (see Fig. 7) within a solder resist layer (70) of a package substrate (100) for an integrated circuit (IC) package, the openings to expose metal pads (524),
and depositing a surface finish (74) onto ones of the metal pads (524) in ones of the openings, the ones of the openings including the first opening, the surface finish (74) including tin. (Fig. 7)
Hsu does not disclose:
a first one of the openings defining a fiducial marker;
However, Lin discloses:
a first one of the openings (213) defining a fiducial marker (per [0043]). (Fig. 3f)
It would Have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hsu in view of Lin for a first one of the openings defining a fiducial marker in order to make “improvements to horizontal and vertical electrical interconnection between multiple semiconductor devices on multiple levels.” (Olin, [0009])
Regarding claim 18, Hsu discloses the method of claim 17, wherein the depositing of the surface finish (74) is accomplished through electroless plating.
From Hsu: “ the surface treatment layer 74 is formed by electroplating gold. It can be understood that the method of forming the surface treatment layer 74 may be replaced by nickel plating gold, nickel immersion gold plating, nickel plating palladium gold plating, tin plating, etc.”
Regarding claim 19, Hsu discloses the method of claim 17, wherein the depositing of the surface finish (74) is accomplished without a rock and shock operation. (there is no mention of this operation in Hsu and therefore the examiner has met the limitation)
Regarding claim 20, Hsu discloses the method of claim 17, further including constructing the package substrate with a glass core (at least 20). (Fig. 7)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Darmawikarta (US 20200411441 A1) discloses package substrate 100 with a layer 115 may be an additional dielectric layer (e.g., a build-up layer, etc.) or a solder resist layer and the contact pads 109 is a die side pad (e.g., a die side capacitor pad, etc.) and a surface finish 113 on the contact pads 109 but does not disclose all the limitations as required by the claim.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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