Prosecution Insights
Last updated: April 19, 2026
Application No. 18/319,248

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103§112
Filed
May 17, 2023
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
2y 8m
To Grant
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allow Rate
488 granted / 793 resolved
-6.5% vs TC avg
Strong +25% interview lift
Without
With
+25.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
52 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 793 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions The application contains claims directed to both a device and a method. At this time Examiner is not requiring a restriction between the two because the method claim is generic to the device claim. If the method claim is amended such that it is no longer generic to the device claim a restriction may issue. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on May 17, 2023 was considered by the examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of claim 2 must be shown or the feature(s) canceled from the claim(s). Regarding claim 2, Claim 1 requires the void to straddle, or be between first trench and second trench. Claim 2 requires all of the limitations of claim 1, which includes the void, and requires the fourth insulation film, IF4, to cover a side surface, and bottom surface of the second trench. Applicant does not have a figure showing this. Figures 9 and 13-14 shows IF4 covering the second trench, but does not include a void. Therefore, there are no figures showing this claimed feature. Regarding claim 2, Claim 2 suffers the same issue as the previous claim 2 above. In that the drawings do not show “a fifth insulating film filled in the first trench and the second trench via the fourth insulating film.” The issue with both of these drawing objections is that Applicant in claim 1 claims the third insulating film has the void. Where the figures show the fifth insulating film IF5 has the void. It appears that Applicant is trying in claim 1 to rename the fifth insulating film to the third insulating film, but then does not correct the name in the dependent claims. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112(a) The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 2, and 9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 2, Claim 2 requires all of the limitations of claim 1, which includes the void, and requires the fourth insulation film, IF4, to cover a side surface, and bottom surface of the second trench. Applicant does not have written description support for the fourth insulating film IF4 to cover the bottom surface and side surface of the second trench D2 at the same time a void V1 straddles between the first trench D1 and the second trench D2. This consistent with Hyatt v. Dudas, 492 F.3d 1365, 1371 (Fed. Cir. 2007), where the court stated: Here, we hold the examiner's initial rejection complied with § 2163.04(I)(B), followed Alton, and accomplished the aims of the prima facie case. For example, in rejecting application claim 163, the examiner explained that the written description did not support the particular claimed combination of elements, even listing each and every element of the allegedly unsupported combination.5 And the examiner was explicit that while each element may be individually described in the specification, the deficiency was the lack of adequate description of their combination—he stated, “While each element may individually be discussed neither the specification nor drawings clearly support the claimed embodiment as a whole.” Id. (emphasis added). He further indicated what Hyatt needed to address his concern: “[I]t is not enough that applicant show where each claimed element resides in the earliest filed application but [he] must also provide support for the linkage of the claimed elements creating the embodiment.” (citations omitted). See MPEP 2163.04, where Examiner has identified the claim limitation and How established a prima facie case by provide the reason why a person skilled in the art at the time of the application was filed would not have recognized that the inventor was in possession of the invention as claimed in view of the disclosure of the application as filed because it appears the specification does not clearly support the claimed embodiment as a whole. Regarding claim 2, Claim 2 suffers the same issue as the previous claim 2 above. In that the limitation “a fifth insulating film filled in the first trench and the second trench via the fourth insulating film.” Appears to lack written description support. The issue with both of these rejections is that Applicant in claim 1 claims the third insulating film has the void. Where the figures show the fifth insulating film IF5 has the void. It appears that Applicant is trying in claim 1 to rename the fifth insulating film to the third insulating film, but then does not correct the name in the dependent claims. Regarding Claim 9, Claim 9 is rejected for the same reason as claim 2 above. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 4, 8, 11 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Yen et al. (US 2019/0148219 A1) (“Yen”). Regarding claims 1, and 8, Yen teaches at least in figure 1-13 a semiconductor substrate (24); a first insulating film (22) formed on the semiconductor substrate (24); a semiconductor layer (20) formed on the first insulating film (22); a first trench (figure 3 a first element 28; hereinafter “28”) penetrated through the semiconductor layer (20) and reached to the first insulating film (22); a second insulating film (30) covered a surface of the first trench (22) and contacted to the first insulating film (22) at a bottom of the first trench (28); a second trench (figure 10B element 502a) formed at the bottom of the first trench (28) such that the second trench (502a) penetrates through the second insulating film (30) and reached in the first insulating film (30); and a third insulating film (70) filled in the first trench (28) and the second trench (502a), wherein the third insulating film (70) has a void (504a-c) such that the void straddles between the first trench and the second trench (¶ 0027, where 504a-c may extend above 22; Examiner interprets the word straddles to mean the void must be between the first trench and the second trench). Regarding claims 4, and 11, Yen teaches at least in figure 1-13: Claims 4 and 11 read on, and are broader than claim 1. Therefore, the claims are rejected for the same reasons give in claims 1 and 8 above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3, 5-7, 10, and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yen. Regarding claims 3, and 10, Yen teaches at least in figure 1-13: a third trench (another 28) formed on an upper surface of the semiconductor layer (20) and adjacent to the first trench (28); and a sixth insulating film (a second 30 or 32) filled in the third trench (another 28), wherein a depth of the third trench is shallower than a depth of the first trench (this would have been obvious based upon standard semiconductor process variation. The claim does not state how much shallower the third trench needs to be than the first trench. Therefore, at a min it only needs to one atom shallower than the first trench. It would have been obvious to one of ordinary skill in the art that every process in semiconductors has a process range. For example etching a trench to a depth of x is actually a depth of x ± y, where y is the process variation for that process. Thus, this limitation would have been obvious to one of ordinary skill in the art before the effective filing date of the current application.). Regarding claims 5, and 12, Yen teaches at least in figure 1-13: wherein a bottom surface of the first trench (here Applicant has taken the D1 and D2 of claim 1 and 8 above and changed it to a combined D1 as shown in figure 15. The prior art’s 28 and 502 can be considered Applicant’s combined D1) is located lower than an interface between the semiconductor layer (20) and the first insulating film (22) in cross-sectional view (the combined D1 is located lower than the interface between 20 and 22), and a distance between the bottom surface of the first trench and the interface of the semiconductor layer and the first insulating film is 0.3 micrometer or more (this is claiming how deep the first trench is going into the second insulating layer. In ¶ 0025, Yen teaches the width of the deep trench, 504, is smaller than 1150 Å (0.15 micrometers), and the aspect ratio is 4.5. Making the depth of the 504 0.675 micrometers or more. Further, Yen teaches the height of the deep trench 504 is measured from the top of the 28. Yen teaches the depth of 28 is 700-900 Å (0.07-0.09 micrometers), and the thickness of the second insulating layer 22 is 1800-2200 Å (0.18-0.22 micrometers). Thus, Yen teaches the depth of the first trench is 0.585 micrometers below the interface of the semiconductor layer and the first insulating film (subtracting the depth of the first trench minus the thickness of 28 which appears to be the same thickness as the semiconductor layer, Thus, Yen teaches the first trench is deeper than the claimed depth. However, the depth of the first trench into the first insulating layer does not appear to be the critical feature of the invention. What appears to be the critical feature of the invention is that the DTI is formed into the BOX layer to ensure that the semiconductor sections bisected by the DTI do not touch. Thus, the claimed depth does not appear to be critical. Further, the prior art appears to fulfil the same function as the claimed feature. Therefore, while the prior art does not teach the claimed length, this appears to be a change in size and/or proportion of the depth of the first trench as the only difference between the prior art and the claimed feature is a recitation of the relative dimension of the claimed device. MPEP 2144.04(IV)(A).). Regarding claims 6, and 13, Yen teaches at least in figure 1-13: wherein a third insulating film (70) has a void (504), and Yen does not explicitly teach: the void (504) has a length that is 80 percent or more of a length of the first trench in cross-sectional view. However, according to ¶ 0027, one can adjust the void length, number, position in the trench, etc. Therefore, while Yen does not explicitly teach the 80 percent or more length it would have been obvious based upon Yen that one could change the size and/or shape of the void based upon the teachings of Yen. Regarding claims 7, and 14, Yen teaches at least in figure 1-13: The limitations of claims 7 and 14 are contained in claims 1 and 8. Therefore, claims 7 and 14 are rejected for the same reasons as claims 4 and 11 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
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Prosecution Timeline

May 17, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+25.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 793 resolved cases by this examiner. Grant probability derived from career allow rate.

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