Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (a device/product made) and Species A (reading on Figs. 1A-1C) in the reply filed on 12/18/2025 is acknowledged.
Claims 7-14 are directed at least to a non-elected Invention (a method). Claim 5 is directed to a non-elected species at least because of the limitation “trenches”. Accordingly, Claims 5 and 7-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and/or Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/18/2025.
Priority
Receipt is acknowledged of a certified copy of foreign application CN 112100175 filed 1/4/2023, however the present application does not properly claim priority to the submitted foreign application. The Application Data Sheet filed 5/17/2023 claims priority to another document which has not been provided (TW 112100175). If this copy is being filed to obtain priority to the foreign filing date under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a), applicant must also file a claim for such priority as required by 35 U.S.C. 119(b) or 365(b), and 37 CFR 1.55. If the application was filed before September 16, 2012, the priority claim must be made in either the oath or declaration or in an application data sheet; if the application was filed on or after September 16, 2012, the claim for foreign priority must be presented in an application data sheet.
If the application being examined is an original application filed under 35 U.S.C. 111(a) (other than a design application), the claim for priority must be presented during the pendency of the application, and within the later of four months from the actual filing date of the application or sixteen months from the filing date of the prior foreign application. See 37 CFR 1.55(d)(1). If the application being examined is a national stage application under 35 U.S.C. 371, the claim for priority must be made within the time limit set forth in the PCT and Regulations under the PCT. See 37 CFR 1.55(d)(2). Any claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) not presented within the time period set forth in 37 CFR 1.55 is considered to have been waived. If a claim for foreign priority is presented after the time period set forth in 37 CFR 1.55, the claim may be accepted if the claim properly identifies the prior foreign application and is accompanied by a grantable petition under 37 CFR 1.55(e) to accept an unintentionally delayed claim for priority and the applicable petition fee under 37 CFR 1.17(m)(1) or (m)(2).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/17/2023 and 12/12/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: “the read transistors is” in lines 12-13. For the sake of compact prosecution, claim 1 is interpreted in the instant Office action as follows: “the read transistors is” is found to be a typographical error because it is intermixing singular and plural phrasing. This term is believed to be equivalent to “the read transistor” based [0030] of the disclosure; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (CN 115274668 A) in view of Yamazaki (WO 2021090106 A1).
Regarding claim 1, Zhu discloses a dynamic random access memory (DRAM) device (pg. 4 of translation: “a dynamic random access memory”), comprising:
a substrate (Fig. 10(b): 1001);
a plurality of write word lines (1051 combined with 1045; pg. 10 : “WWL”), extending toward a first direction (X direction, See annotated figure);
a plurality of write bit lines (1021; pg. 10: “WBL”), extending toward a second direction (Y direction), wherein the second direction is orthogonal to the first direction (“orthogonal” is shown by Fig. 10(c): 1051 and Fig. 10(b): 1021. Note: these figures are on the A-A’ and B-B’ cross sections respectively, which are shown earlier as orthogonal; See Fig. 3(a) for reference lines);
a plurality of read word lines (1015; pg. 10: “RWL”), extending toward the first direction (shown in Fig. 10(c));
a plurality of read bit lines (1005; pg. 10: “RBL”), extending toward the second direction;
and a [memory device layer] (the collective assembly of sub-layers from 1003 to 1051 with all intervening layers; See dashed reference lines marking the memory device layer), disposed on the substrate (the collection is directly on substrate 1001) and stacked in a normal direction of the substrate (Z direction), wherein [the memory device layer] comprises a plurality of memory cells (Figs. 10(b) and 10(c) collectively show a 2x4 array of 8 cells), the plurality of memory cells comprise write transistors (pg. 10: “TW”; schematically shown in Fig. 15) and read transistors (pg. 10: “TR”; schematically shown in Fig. 15), the write transistor is electrically connected to a corresponding write word line (Fig. 15 shows TW connected to WWL at the gate terminal) and a corresponding write bit line (Fig. 15 shows TW connected to WBL at a source/drain terminal), and the read transistors is electrically connected to a corresponding read word line (Fig. 15 shows TR connected to RWL at a source/drain terminal) and a corresponding read bit line (Fig. 15 shows TR connected to RBL at another source/drain terminal), wherein a source of the write transistor is electrically connected to a gate of the read transistor (Fig. 15 shows a direct connection at SN) to form a storage node (SN; pg. 10: “a storage node SN”).
Illustrated below are marked and annotated figures of Fig. 10(b) and Fig. 15 of Zhu.
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Zhu teaches the plurality of memory cells formed in the memory device layer; however, fails to teach pluralizing the number of memory device layers. Thus, Zhu fails to teach “a plurality of memory device layers, disposed on the substrate and stacked in a normal direction of the substrate, wherein each of the plurality of memory device layers comprises a plurality of memory cells”.
Yamazaki teaches a plurality of memory cells (Fig. 23B, a sub-assembly; pg. 60 of translation: “a cell array”) formed in a memory device layer (Fig. 24; 610_1) configured as a plurality of memory device layers (additional 610 layers are shown such as 610_n), disposed on the substrate (not illustrated in the collection of sub-assemblies of Fig. 24, however; pg. 23: “the substrate on which the transistor 200 is formed” and Fig. 25: 411 teach the substrate arrangement) and stacked in a normal direction of the substrate (Fig. 24: 610 are stacked in the same way as Fig. 25: 415, which are stacked in “a normal direction of the substrate”), wherein each of the plurality of memory device layers comprises a plurality of memory cells (Fig. 23B: 600 and 601; pg. 60 : “cells”).
Modifying the memory device layer of Zhu by duplicating its parts in the same way disclosed by Yamazaki would arrive at the claimed configuration of the plurality of memory device layers. A person of ordinary skill in the art before the effective filing date would have had predictable results duplicating the memory device layer, because Yamazaki teaches duplication is a known alternative configuration of a single layer (pg. 60: “the above-mentioned cell array may be laminated as well as flat”). Yamazaki provides a teaching to motivate one of ordinary skill in the art to duplicate the memory device layer in that it would enable a compact device by increasing memory capacity without requiring a large footprint (pg. 60 : “by stacking a plurality […], cells can be integrated and arranged without increasing the occupied area of the cell array”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed plurality of memory device layers because it is a duplication of parts that would advantageously enable a compact device. MPEP 2143 (I)(G). MPEP 2144.04 (VI)(B).
Illustrated below is Fig. 24 of Yamazaki.
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484
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Regarding claim 2, Zhu in view of Yamazaki discloses the DRAM device according to claim 1 (Zhu: Fig. 10(b)), wherein materials of a channel layer of the write transistor (1041; pgs. 10-11: “The second transistor may be similarly formed…a conductive material”; pg. 5: “may include a semiconductor material”; pg. 9: “may include an oxide semiconductor”) and a channel layer of the read transistor (1027; pg. 9: “may include an oxide semiconductor”) comprise oxide semiconductors.
Regarding claim 3, Zhu in view of Yamazaki discloses the DRAM device according to claim 2 (Zhu: Fig. 10(b)), wherein the channel layer of the write transistor and the channel layer of the read transistor extend toward the normal direction of the substrate (each of 1041 and 1027 extend in the Z direction).
Regarding claim 4, Zhu in view of Yamazaki discloses the DRAM device according to claim 1 (Zhu: Fig. 10(b)), wherein the plurality of write word lines are disposed on the substrate (indirectly on).
Regarding claim 6, Zhu in view of Yamazaki discloses the DRAM device according to claim 1 (Zhu: Fig. 10(b)), wherein a drain of the write transistor (a portion of 1041) and the write bit line belong to the same layer (these features are directly adjacent in the Y direction and thus “belong to the same level”), and a drain of the read transistor (a portion of 1027) and the read bit line belong to the same layer (these features are directly adjacent in the Y direction and thus “belong to the same level”).
Conclusion
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817