Prosecution Insights
Last updated: April 19, 2026
Application No. 18/319,428

ENHANCEMENT MODE SWITCHING DEVICES AND MANUFACTURING METHODS THEREOF

Non-Final OA §102§103
Filed
May 17, 2023
Examiner
MCCUTCHEON, COLIN RUSSELL
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Enkris Semiconductor Inc.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
29 granted / 36 resolved
+12.6% vs TC avg
Strong +27% interview lift
Without
With
+26.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
24 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§103
66.2%
+26.2% vs TC avg
§102
25.1%
-14.9% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 36 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions & Claims’ Status Applicant's election with traverse of Group I, Species 1a in the reply filed on 11/12/2025 is acknowledged. No specific arguments were provided with the traversal, so no response here is given. The requirement is still deemed proper and is therefore made FINAL. Claims 13-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/12/2025. Claims 1-16 are currently pending. Claim 14 has been amended. No claims have been cancelled or newly added. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 5/17/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nongaillard et al (US 2021/0202728 A1, hereafter Nongaillard). Re Claim 1, Nongaillard discloses an enhancement mode switching device (FIG. 3a; [0063]-[0073]), comprising: a substrate (“support substrate”, would be under channel structure 1; [0086]); a channel structure (1; [0036]), comprising a channel layer (1b; [0036]) and a barrier layer (1a; [0036]), wherein the channel layer (1b) is provided on the substrate (“support substrate”; [0086]), and the barrier layer (1a) is provided on a side of the channel layer (1b) far away from the substrate (“support substrate”; [0036]); a side of the channel structure (1, top side; [0036]) far away from the substrate (“support substrate”) is provided with a trench (5; [0088]), the trench (5) penetrates through the barrier layer (1a) and a part of the channel layer (1b; [0088]); the channel structure (1) comprises a source region (1, region contacting 20; [0039]), a drain region (1, region contacting 30; [0039]), and a gate region (1, region below 40; [0041]) between the source region (1, region contacting 20) and the drain region (1, region contacting 30; [0041]); and the trench (5) is located in the gate region (1, region below 40; [0088]); a p-type semiconductor layer (4a; [0063]) in the gate region (1, region below 40; [0089]), wherein at least of part of the p-type semiconductor layer (4a) is located in the trench (5; [0089]) and is in contact with the channel layer (1b; [0055], thermal contact, particularly when 4e layer is AlN); a gate electrode (40; [0041]), located on a side of the p-type semiconductor layer (4a) far away from the substrate (“support substrate”; [0041]); a source electrode (20; [0039]), located in the source region (1, region contacting 20; [0039]); and a drain electrode (30; [0039]), located in the drain region (1, region contacting 30; [0039]). Re Claim 2, Nongaillard discloses the device according to Claim 1, while further disclosing wherein the channel layer (1b) is an n-type semiconductor ([0037]); or, a part of the channel layer (1b) exposed by the trench (5) is an n-type semiconductor ([0037]). Re Claim 3, Nongaillard discloses the device according to Claim 1, while further disclosing the device comprises an n-type semiconductor layer (4b; [0065]), covering a bottom wall of the trench (5; [0065]), wherein the p-type semiconductor layer (4a) is provided on the n-type semiconductor layer (4b; [0065], on the bottom of). Re Claim 4, Nongaillard discloses the device according to Claim 1, while further disclosing the device comprises an n-type semiconductor layer (4b; [0065]), covering a bottom wall and sidewalls of the trench (5; [0065], covers bottom wall in vertical direction, partially covers sidewalls in horizontal direction), wherein the p-type semiconductor layer (4a) is provided on the n-type semiconductor layer (4b; [0065], on the bottom of). Re Claim 5, Nongaillard discloses the device according to Claim 3, while further disclosing wherein a material of the n-type semiconductor layer (4b) is selected from one or more of n-type GaN ([0066]), n-type AlGaN or n-type InGaN. Re Claim 7, Nongaillard discloses the device according to Claim 1, while further disclosing wherein a material of the p-type semiconductor layer (4a) is selected from one or more of p-type GaN ([0066]), p-type AlGaN or p-type InGaN. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nongaillard, as applied to Claim 1, in view of Bisi et al (US 2023/0299190 A1, hereafter Bisi). Re Claim 6, Nongaillard discloses the device according to Claim 1, but does not explicitly disclose wherein a doping concentration of p-type doped ions in the p-type semiconductor layer (4a) is varied, and a variation pattern of the doping concentration of the p-type doped ions varying from bottom to up comprises one of or a combination of two or more of the following variation patterns: gradual increasing, gradual decreasing, stepwise increasing, stepwise decreasing, or periodic changing. However, Bisi teaches a device (FIG. 2; [0031]-[0052]) comprising wherein a doping concentration of p-type doped ions in the p-type semiconductor layer (16; [0039]) is varied ([0039]), and a variation pattern of the doping concentration of the p-type doped ions varying from bottom to up ([0039]) comprises one of or a combination of two or more of the following variation patterns: gradual increasing, gradual decreasing, stepwise increasing, stepwise decreasing, or periodic changing ([0039]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device discussed for Claim 1 with the limitations taught by Bisi to utilize the doping profiles of Bisi to optimize for the areal density of ionized negative charge as taught by Bisi ([0041]) and supported by Nongaillard ([0008]). Re Claim 8, Nongaillard discloses the device according to Claim 1, but does not explicitly disclose wherein the p-type semiconductor layer (4a) comprises at least one element with changing composition, content of the element with changing composition changes in the epitaxial direction, and a variation curve of the content of the element with changing composition in the epitaxial direction includes one of or a combination of two or more of the following variation stages: periodic variation, increasing variation or decreasing variation. However, Bisi teaches a device (FIG. 2; [0031]-[0052]) wherein the p-type semiconductor layer (16; [0039]) comprises at least one element with changing composition ([0039], the p-type dopant), content of the element with changing composition changes in the epitaxial direction ([0039]), and a variation curve of the content of the element with changing composition in the epitaxial direction includes one of or a combination of two or more of the following variation stages: periodic variation ([0039], via being repeated), increasing variation or decreasing variation. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device discussed for Claim 1 with the limitations taught by Bisi to utilize the doping profiles of Bisi to optimize for the areal density of ionized negative charge as taught by Bisi ([0041]) and supported by Nongaillard ([0008]). Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Nongaillard, as applied to Claim 1, in view of Zhu et al (WO 2020/252626 A1, hereafter Zhu). Re Claim 10, Nongaillard discloses the device according to Claim 1, but does not explicitly disclose wherein the trench (5) comprises a plurality of discrete sub-trenches. However, Zhu teaches a device (FIG. 2a; pg. 3, paras. 6-11) wherein the trench (3; pg. 3, para. 10) comprises a plurality of discrete sub-trenches (3; pg. 3, para. 10). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device discussed for Claim 1 with the limitations taught by Zhu to utilize a plurality of discrete sub-trenches (Zhu: 3) to increase the scope of the channel depletion effect as taught by Zhu (pg. 3, paras. 10-11). Re Claim 11, Nongaillard discloses the device according to Claim 1, but does not explicitly disclose the device comprises a cap layer, wherein the cap layer is provided on a side of the barrier layer (1a) far away from the substrate (“support substrate”), and the cap layer is provided with an opening connecting with the trench (5). However, Zhu teaches a device (FIG. 12d; pg. 4, para. 10) that comprises a cap layer (5; pg. 4, para. 3), wherein the cap layer (5) is provided on a side of the barrier layer (24; pg. 4, para. 3) far away from the substrate (1; pg. 4, para. 3), and the cap layer (5) is provided with an opening connecting with the trench (3; pg. 4, para. 10). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device discussed for Claim 1 with the limitations taught by Zhu to utilize a cap layer (Zhu: 5) above the barrier layer (Nongaillard: 1a) with an opening connecting to the trench (Nongaillard: 5) to directly connect the gate electrode (Nongaillard: 40) to the underlying semiconductor material (Nongaillard: 4a/4b) while provided electrical isolation as taught by Zhu (pg. 4, para. 10). Allowable Subject Matter Claims 9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Re Claim 9, the prior art cannot anticipate or render obvious the limitations of: the content of the element with changing composition increases uniformly in the first periodic layer and decreases uniformly in the second periodic layer; the content of the element with changing composition decreases uniformly in the first periodic layer and increases uniformly in the second periodic layer; […] wherein the first content is higher or lower than the second content, in combination with the additionally claimed features of Claim 9. Re Claim 12, the prior art cannot anticipate or render obvious the limitations of: the cap layer and the n-type semiconductor layer are integrally formed, in combination with the additionally claimed features of Claim 12. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

May 17, 2023
Application Filed
Jan 26, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+26.9%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 36 resolved cases by this examiner. Grant probability derived from career allow rate.

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