DETAILED ACTION
This Office Action is in response to RCE filed September 3, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Murakawa et al. (WO 2020/262560) (Murakawa et al. (US 2022/0415714) is used as a translation in current Office Action) in view of Kunisato et al. (US 2002/0127856)
The Examiner notes that, by removing the limitation “the first opening is an oblique columnar opening having a vertical section that is an inclined parallelogram” in the amended claim 1 in the amendment filed September 3, 2026, which is exactly the same limitation that Applicants added in the amendment filed May 18, 2026 in addition to the word “and”, the amendment filed September 3, 2026 is substantially identical to original claim 1 except for the additional word “and” for which the Examiner made the prior art rejection over Murakawa et al. in view of Kunisato et al. in the Non Final Office Action mailed February 18, 2026.
Regarding claim 1, Murakawa et al. disclose a manufacturing method of a semiconductor structure (Fig. 9), comprising: providing a structure (Fig. 5) to be peeled off, wherein the structure to be peeled off comprises a first structure (structure including and disposed below mask layer 18 in Fig. 5) and a second structure (structure disposed above mask layer 18 in Fig. 5), the first structure comprises: a base (11) ([0045]); a first mask layer (18) ([0055]) located on the base, wherein a first opening (18b) ([0060]) that exposes the base is provided in the first mask layer, see Fig. 1, the first opening comprises an open end (top portion of opening portion 18b in Fig. 1); and a first epitaxial layer (bottom portion of 13 inside opening portion 18b) ([0059]) epitaxially grown from the base (11) to fill up the first opening (18b), because Applicants’ first epitaxial layer 12 is also formed inside the first opening 110/111 in Fig. 16 of current application; and the second structure comprises: a second epitaxial layer (top portion of 13 (and subsequently deposited layer(s) including n-type GaN layer)) ([0064]) located on the first epitaxial layer and the first mask layer; and applying force ([0071]) on the structure to be peeled off to fracture the second epitaxial layer and the first epitaxial layer (bottom portion of 13 inside opening portion 18b) (Fig. 7), to peel off the first structure and make the second structure form a semiconductor structure, because (a) Murakawa et al. disclose that “Since each element portion 12 is peeled off from the underlying substrate 11, each connection portion 23 is broken (emphasis added)”, and that “Such a connection portion 23 may remain at the underlying substrate 11 side or the element portion 12 side or both of them, depending on the situation of breakage”, (b) Applicants do not specifically claim where the claimed fracture is generated, (c) for example, when strictly interpreted, Figs. 21 and 22 of current application show that the fracture is generated only inside the first epitaxial layer 12 rather than inside both the first epitaxial layer 12 and the second epitaxial layer 21 shown in Fig. 17 of current application, and (d) therefore, the limitation “to fracture the second epitaxial layer and the first epitaxial layer” should be broadly interpreted since otherwise claim 1 would be indefinite.
Murakawa et al. differ from the claimed invention by not showing that an area of an orthographic projection of the open end on the base is less than an area of an orthographic projection of the first opening on the base.
Kunisato et al. disclose a manufacturing method of a semiconductor structure, where an area of an orthographic projection of an open end (top portion of opening of first mask layer 2) of a first mask layer (2 in Fig. 1) ([0064]) on a base (1) is less than an area of an orthographic projection of a first opening (bottom portion of opening of first mask layer 2) of the first mask layer (area between overhangs 2a) on the base.
Since both Murakawa et al. and Kunisato et al. teach a manufacturing method of a semiconductor structure employing a mask layer, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an area of an orthographic projection of the open end on the base disclosed by Murakawa et al. can be less than an area of an orthographic projection of the first opening on the base of Murakawa et al. as disclosed by Kunisato et al., because (a) as disclosed in paragraph [0024] of Kunisato et al., i.e. “the nitride-based semiconductor layer, having low dislocation density, consisting of the material different from that of the underlayer can be grown on the underlayer with a small thickness to form hetero structure”, and “the mask layers are preferably at least partially inverse-trapezoidal”, (b) the inverse-trapezoidal mask layer disclosed by Kunisato et al. would improve the quality of the semiconductor layers grown on the first mask layer disclosed by Murakawa et al., which in turn would improve performance of the semiconductor device formed by using the higher quality semiconductor layers.
Regarding claim 3, Murakawa et al. further disclose that before applying the force on the structure to be peeled off (Figs. 5 and 6), the manufacturing method further comprises removing the first mask layer (18 in Figs. 1 and 5) in the first structure.
Murakawa et al. in view of Kunisato et al. differ from the claimed invention by not showing that the first mask layer is removed by wet etching.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first mask layer 18 disclosed by Murakawa et al. can be removed by wet etching, because (a) dry etching and wet etching, which are basically only two types of etchings, have been commonly and interchangeably employed in semiconductor research and industry, and (b) the first mask layer 18 disclosed by Murakawa et al. disposed underneath a device structure disclosed by Murakawa et al. has been commonly etched by wet etching since wet etching can remove dielectric or semiconductor materials that dry etching may not be able to remove since etchant for wet etching can flow in an area that is not easily accessible and not directly in line of sight by dry etching.
Regarding claims 9-11, Murakawa et al. further disclose that the second structure comprises a transfer substrate (support substrate 14 in Fig. 6 after support substrate 14 is bonded to underlying structure) ([0069]); before applying force on the structure to be peeled, the manufacturing method further comprises: adhering or bonding a surface of the second epitaxial layer (top portion of 13 (and subsequently deposited layer(s)) away from the first epitaxial layer (bottom portion of 12) to the transfer substrate (step between Fig. 6 and Fig. 7); and when force is applied to the second structure, the force is applied to the transfer substrate, which is an inherent process to obtain the semiconductor device structure shown in Fig. 7 of Murakawa et al. (claim 9), a plurality of first openings (18b in Fig. 1) ([0057]) are provided, and a second epitaxial layer (top portion of 13 (and subsequently deposited layer(s)) in Figs. 2 and 3) corresponding to each of the plurality of the first openings is coalesced into a plane (top surface of 13 (and subsequently deposited layer(s)) in Figs. 2 and 3) (claim 10), and a plurality of first openings (18b in Fig. 1) are provided, and the second epitaxial layer (top portion of 13 (and subsequently deposited layer(s)) in Figs. 2 and 3) corresponding to each of the plurality of the first openings is an LED structure or a vertically conductive semiconductor structure (Fig. 4) ([0052] and [0067]) (claim 11).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Murakawa et al. (US 2025/0112439)
Musaki et al. (US 12,132,142)
Sumida et al. (US 2012/0280363)
Misaki et al. (US 12,550,674)
Kuo (US 11,152,540)
Kamikawa et al. (US 12,205,847)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 September 28, 2026
