Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the 20claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Lei et al. (US 2015/0079761, hereinafter Lei).
With respect to claim 14, Lei discloses a method of forming devices comprising: providing a wafer (204 of Fig. 2D), wherein the wafer comprises a first major wafer surface (top of 204), wherein the first major surface is an active wafer surface (top surface is an active surface),
a second major wafer surface (bottom surface of 204), wherein the second major surface is an inactive wafer surface (Fig. 2D); and
forming a passivation stack on the first major wafer surface (stack of layer on the top of 204): forming a mask layer on the second major wafer surface (252);
patterning the passivation stack on the first major wafer surface to form a patterned passivation stack with openings corresponding to dicing channels (Fig. 2D – patterning the stack on the top side of the wafer);
patterning the mask layer to form a patterned mask layer with openings corresponding to dicing channels (patterning layer 252);
plasma dicing the wafer using the patterned mask layer from the second major wafer surface to singulate the wafer into individual dies (Para 0021-0022 and 0024).
Lei in the same embodiment does not explicitly disclose that the dicing channels are in x and y directions.
In another embodiment, Lei discloses that that the dicing channels are in x and y directions (Fig. 4 – dicing streets/scribing lines 335 are in x & y directions). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s first embodiment by having dicing channels are in x and y directions in order to expedite the singulation process.
With respect to claim 29, Lei discloses a method of forming devices comprising: providing a wafer (204 of Fig. 2D), with a plurality of active dies (206’s) wherein the wafer comprises a first major active wafer surface (top of 204),
a second major inactive wafer surface (bottom surface of 204); and
forming a passivation stack on the first major active wafer surface (stack of layer on the top of 204): forming a mask layer on the second major inactive wafer surface (252);
patterning the passivation stack to form a patterned passivation stack with passivation stack openings (Fig. 2D) corresponding to dicing channels (Fig. 2D – patterning the stack on the top side of the wafer) the dicing channels separate the active dies (Fig. 2E);
patterning the mask layer to form a patterned mask layer with mask openings corresponding to dicing channels (patterning layer 252 of Fig. 2D);
plasma dicing the wafer from the second major inactive wafer surface using the patterned mask layer (Para 0021-0022 and 0024), wherein plasma dicing the wafer comprises plasma dicing the wafer partially (Fig. 2D) leaving a remainder portion to singulate the wafer into individual active dies (Fig. 2D).
Lei in the same embodiment does not explicitly disclose that the dicing channels are in x and y directions.
In another embodiment, Lei discloses that that the dicing channels are in x and y directions (Fig. 4 – dicing streets/scribing lines 335 are in x & y directions). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s first embodiment by having dicing channels are in x and y directions in order to expedite the singulation process.
Claims 16-17 and 20-21, 30-33 are rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Jeon et al. (US 2020/0098635, hereinafter Jeon).
With respect to claim 16, Lei discloses the method of claim 14.
Lei discloses wherein plasma dicing the wafer comprises plasma dicing the wafer from the first and second major surfaces (Fig. 2D).
Lei does not explicitly disclose that the plasma dicing forms scalloped-shaped die sidewalls for dies of the wafer.
In an analogous art, Jeon discloses that the plasma dicing forms scalloped-shaped die sidewalls for dies of the wafer (Para 0087-0088). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 17, Lei discloses the method of claim 14.
Lei discloses plasma dicing the wafer partially from the second major wafer surface, leaving a remainder portion below the patterned passivation stack on the first major wafer surface (Fig. 2D).
Lei does not explicitly disclose wherein plasma dicing forms scalloped-shaped die sidewalls; and force breaking the remainder portion to singulate the wafer into individual dies, wherein force breaking forms a foot portion in the remainder portion which extends out from the scalloped-shaped die sidewalls.
In an analogous art, Jeon discloses wherein plasma dicing the wafer comprises plasma dicing the wafer partially (Fig. 4B, 5), leaving a remainder portion (Fig. 8A-8G),
the plasma dicing forms scalloped-shaped die sidewalls (Fig. 4B, 5 and 8G); and force breaking the remainder portion to singulate the wafer into individual dies (Para 0065 and 0073-0074), wherein force breaking forms a foot portion in the remainder portion which extends out from the scalloped-shaped die sidewalls (Fig. 2A- 2E & Fig. 7). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 20, Lei/Jeon discloses the method of claim 17.
Lei does not explicitly disclose wherein force breaking forms the foot portion in the remainder portion with a vertical sidewall.
In an analogous art, Jeon discloses wherein force breaking forms the foot portion in the remainder portion with a vertical sidewall (Fig. 2A-2C). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 21, Lei discloses wherein a thickness of the remainder portion is about 10-20% of a thickness of the water (Fig. 2D).
With respect to claim 30, Lei discloses the method of claim 29.
Lei discloses wherein plasma dicing the wafer comprises plasma dicing the wafer from the second major wafer surface through the first major wafer surface (Fig. 2D).
Lei does not explicitly disclose that the plasma dicing forms scalloped-shaped die sidewalls for dies of the wafer.
In an analogous art, Jeon discloses that the plasma dicing forms scalloped-shaped die sidewalls for dies of the wafer (Para 0087-0088). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 31, Lei discloses the method of claim 29.
Lei discloses plasma dicing the wafer partially from the second major wafer surface, leaving a remainder portion below the patterned passivation stack on the first major wafer surface (Fig. 2D).
Lei does not explicitly disclose wherein plasma dicing forms scalloped-shaped die sidewalls; and force breaking the remainder portion to singulate the wafer into individual dies, wherein force breaking forms a foot portion in the remainder portion which extends out from the scalloped-shaped die sidewalls.
In an analogous art, Jeon discloses wherein plasma dicing the wafer comprises plasma dicing the wafer partially (Fig. 4B, 5), leaving a remainder portion (Fig. 8A-8G),
the plasma dicing forms scalloped-shaped die sidewalls (Fig. 4B, 5 and 8G); and force breaking the remainder portion to singulate the wafer into individual dies (Para 0065 and 0073-0074), wherein force breaking forms a foot portion in the remainder portion which extends out from the scalloped-shaped die sidewalls (Fig. 2A- 2E & Fig. 7). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 32, Lei discloses wherein a thickness of the remainder portion is about 10-20% of a thickness of the water (Fig. 2D).
With respect to claim 33, Lei/Jeon discloses the method of claim 31.
Lei does not explicitly disclose wherein force breaking forms the foot portion in the remainder portion with a vertical sidewall.
In an analogous art, Jeon discloses wherein force breaking forms the foot portion in the remainder portion with a vertical sidewall (Fig. 2A-2C). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Koey (US 8,765,527, hereinafter Koey).
With respect to claim 18, Lei discloses the method of claim 14.
Lei discloses dicing channels in x and y directions separate the dies (Fig. 4).
Lei does not explicitly disclose that the dies are active dies and wherein the wafer comprises a processed wafer with a plurality of active dies; and wherein the wafer is singulated into individual active dies.
In an analogous art, Koey discloses that the dies are active dies (Col. 6, lines 50-53) and wherein the wafer comprises a processed wafer with a plurality of active dies, wherein singulating the wafer into individual dies singulates the wafer into individual active dies (Col. 6, lines 50-53; singulating an active wafer into active dies).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Koey’s disclosure in order to provide circuits to manufacture a semiconductor device.
Claims 19, 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lei/Koey in view of Mou et al. (US 2019/0206676, hereinafter Mou).
With respect to claim 19, Lei/Koey discloses the method of claim 18.
Lei/Koey does not explicitly disclose wherein the processed wafer with the plurality of active dies includes circuit components; a back-end-of-line (BEOL) dielectric layer with interconnects over the circuit components, and the passivation stack disposed on a top surface of the BEOL dielectric layer.
In an analogous art, Mou discloses wherein the processed wafer with the plurality of active dies includes circuit components (Para 0005), a back-end-of-line (BEOL) dielectric layer (260 of Fig. 2a) with interconnects over the circuit components (Para 0005 and 0024), and the passivation stack (272 & 274) disposed on a top surface of the BEOL dielectric layer (Fig. 2a – stack of 272 & 274 is disposed on 260).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei/Koey’s method by having Mou’s disclosure in order to protect and insulate components of a semiconductor device.
With respect to claim 22, Lei/Koey/Mou discloses the method of claim 19.
Lei/Koey does not explicitly disclose wherein the BEOL dielectric layer includes a pre-metal interlayer dielectric (ILD) layer disposed over the circuit components; and a plurality of intermetal dielectric (MD) layers disposed over the pre-metal ILD layer.
In an analogous art, Mou discloses wherein the BEOL dielectric layer includes a pre-metal interlayer dielectric (ILD) layer disposed over the circuit components (Para 0024); and a plurality of intermetal dielectric (MD) layers disposed over the pre-metal ILD layer (Para 0033; plurality of ILD levels). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei/Koey’s method by having Mou’s disclosure in order to protect and insulate components of a semiconductor device.
With respect to claim 23, Lei/Koey/Mou discloses the method of claim 19.
Lei/Koey does not explicitly disclose wherein the passivation stack comprises multiple dielectric passivation layers.
In an analogous art, Mou discloses wherein the passivation stack comprises multiple dielectric passivation layers (Para 0024-0025; passivation layer may include multiple layer comprising of polyimide). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei/Koey’s method by having Mou’s disclosure in order to protect a semiconductor device during processing.
Claims 24-25, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Lei/Koey/Mou in view of Jeon.
With respect to claim 24, Lei/Koey/Mou discloses the method of claim 19.
Lei discloses wherein plasma dicing the wafer comprises plasma dicing the wafer from the first and second major surfaces (Para 0031).
Lei/Koey/Mou does not explicitly disclose that the plasma dicing forms scalloped-shaped die sidewalls for dies of the wafer.
In an analogous art, Jeon discloses that the plasma dicing forms scalloped-shaped die sidewalls for dies of the wafer (Para 0087-0088). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei/Koey/Mou’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 25, Lei/Koey/Mou discloses the method of claim 19.
Lei/Koey/Mou does not explicitly disclose wherein plasma dicing the wafer comprises plasma dicing the wafer partially, leaving a remainder portion, the plasma dicing forms scalloped-shaped die sidewalls; and force breaking the remainder portion to singulate the wafer into individual active dies, wherein force breaking forms a foot portion in the remainder portion which extends out from the scalloped-shaped die sidewalls.
In an analogous art, Jeon discloses wherein plasma dicing the wafer comprises plasma dicing the wafer partially (Fig. 4B, 5), leaving a remainder portion (Fig. 8A-8G),
the plasma dicing forms scalloped-shaped active die sidewalls (Fig. 4B, 5 and 8G ); and force breaking the remainder portion to singulate the wafer into individual dies (Para 0065 and 0073-0074), wherein force breaking forms a foot portion in the remainder portion which extends out from the scalloped-shaped die sidewalls (Fig. 2A- 2E & Fig. 7). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei/Koey/Mou’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 27, Lei/Koey/Mou/Jeon discloses the method of claim 25.
Lei/Koey/Mou does not explicitly disclose wherein force breaking forms the foot portion in the remainder portion with a vertical sidewall.
In an analogous art, Jeon discloses wherein force breaking forms the foot portion in the remainder portion with a vertical sidewall (Fig. 2A-2C). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei/Koey/Mou’s method by having Jeon’s disclosure in order to expedite the dicing process while protecting the device.
With respect to claim 28, Lei/Koey/Mou/Jeon discloses the method of claim 25.
Lei discloses wherein a thickness of the remainder portion is about 10-20% of a thickness of the water (Fig. 2D).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Mou et al. (US 2019/0206676, hereinafter Mou).
With respect to claim 19, Lei discloses the method of claim 29.
Lei does not explicitly disclose wherein the processed wafer with the plurality of active dies includes circuit components; a back-end-of-line (BEOL) dielectric layer with interconnects over the circuit components, and the passivation stack disposed on a top surface of the BEOL dielectric layer.
In an analogous art, Mou discloses wherein the processed wafer with the plurality of active dies includes circuit components (Para 0005), a back-end-of-line (BEOL) dielectric layer (260 of Fig. 2a) with interconnects over the circuit components (Para 0005 and 0024), and the passivation stack (272 & 274) disposed on a top surface of the BEOL dielectric layer (Fig. 2a – stack of 272 & 274 is disposed on 260).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lei’s method by having Mou’s disclosure in order to protect and insulate components of a semiconductor device.
Allowable Subject Matter
Claim 26 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 26, none of the prior art on record disclose or render obvious the claimed limitation including “wherein the foot portion comprises passivation stack sidewalls and an upper portion of the BEOL dielectric layer” when considered as a whole along with other claimed limitations.
Response to Arguments
Based on new ground of rejection, applicant’s arguments regarding amended claims are moot.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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