Prosecution Insights
Last updated: April 19, 2026
Application No. 18/319,480

LED PACKAGE DEVICE AND PACKAGING METHOD

Final Rejection §103
Filed
May 18, 2023
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen Yunmixin Display Technology Co. Ltd.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 1m
To Grant
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
1105 granted / 1312 resolved
+16.2% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
68 currently pending
Career history
1380
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
21.1%
-18.9% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1312 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US Publication No.2019/0245122) in view of Ibbetson et al (US Publication No. 2005/0093430). Regarding claims 1 and 3, Fan discloses an LED package device and a method, comprising an LED chip Fig 3, 2 and a transparent groove Fig 3, 5 (0043-0045), wherein a quantum dot layer Fig 3, 3 is provided inside the transparent groove Fig 3, 5, a barrier film layer Fig 3, 42 is provided on the quantum dot layer Fig 3, 3, side walls of the barrier film layer are connected and sealed with side walls of the transparent groove Fig 3, the transparent groove Fig 3, 5 is inverted. Fan discloses all the limitations except for the arrangement of the transparent groove relative to a sealing adhesive. Whereas Ibbetson discloses an LED package device Fig 3-4, comprising a substrate Fig 3, 14, an LED chip Fig 3, 12 arranged on the substrate Fig 3, 14 and a transparent groove Fig 3, 40, the substrate Fig 3, 14 being provided with a sealing adhesive layer Fig 3, 19 ¶ 0034, 0050 for cladding the LED chip ¶0034 and 0050; and a phosphor layer ¶0059 is further provided; the transparent groove is inverted on the sealing adhesive layer and connected with the sealing adhesive layer Fig 3-4, and an opening of the transparent groove is sealed by the sealing adhesive layer to cover the layers Fig 3-4. Fan and Ibbetson are analogous art because they are directed to LED package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fan because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Fan to improve device efficiency. Regarding claim 2, Ibbetson discloses wherein one side of the phosphor layer is connected with the barrier film layer, and another side of the phosphor layer is connected with the sealing adhesive layer Fig 3-4. Regarding claim 4, Ibbetson discloses wherein said providing a transparent groove comprises: dispensing a mixture of conversion material and adhesives on a bottom of the transparent groove by a dispensing process to form the conversion material layer ¶0068. Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US Publication No.2019/0245122) in view of Ibbetson et al (US Publication No. 2005/0093430) and in further view of Li et al (US Publication No. 2020/0075817). Regarding claim 5, Fan and Ibbetson disclose all the limitations but silent on the process of forming the quantum dot layer. Whereas Li discloses wherein said providing a transparent groove further comprises: forming the barrier film layer on the quantum dot layer and on the side walls of the transparent groove by an evaporation process or a magnetron sputtering process ¶0076 so that the side walls of the barrier film layer are connected and sealed with the side walls of the transparent groove Fig 4. Fan and Li are analogous art because they are directed to LED package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fan because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the process of Fan and incorporate the teachings of Li as an alternative method known in the art to ease the process step. Regarding claim 6, Li discloses wherein the barrier film layer is made of silicon oxide ¶0076. Regarding claim 7, Li discloses wherein one side of the phosphor layer is connected with the barrier film layer, and another side of the phosphor layer is connected with the sealing adhesive layer Fig 4 ¶0054 and 0056. Regarding claim 8, Li discloses wherein the phosphor layer is formed by a dispensing process ¶0013, 0062-0064. Regarding claim 9, Li discloses wherein the LED chip is a blue LED chip, the phosphor layer is a red phosphor layer, and the quantum dot layer is a green quantum dot layer ¶0034-0036. Regarding claim 10, Ibbetson discloses wherein the transparent groove is made of glass ¶0045 and Claim 6 and 7. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

May 18, 2023
Application Filed
Jul 24, 2025
Non-Final Rejection — §103
Sep 29, 2025
Response Filed
Nov 19, 2025
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604723
Metal Capping Layer for Reducing Gate Resistance in Semiconductor Devices
2y 5m to grant Granted Apr 14, 2026
Patent 12593498
SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12588244
SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION THEREOF
2y 5m to grant Granted Mar 24, 2026
Patent 12588270
METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS
2y 5m to grant Granted Mar 24, 2026
Patent 12581923
METHOD FOR REMOVING EDGE OF SUBSTRATE IN SEMICONDUCTOR STRUCTURE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.1%)
2y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 1312 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month