DETAILED ACTION
This Office action responds to the Amendment file on December 11, 2025 responding to the Office action mailed on September 22, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claims filed on December 11, 2025 have been considered, but are moot in view of the new grounds of rejections as necessitated by applicant’s amendments to the claims.
Hagimoto et al. (US 2016/0141267) teaches a portion of titanium oxide 36B between upper Cu layer 33A plus titanium layer 35A and the dielectric layer 32B. Amanapu et al. (US 10,204,829) teaches manganese atoms being diffused to the dielectric layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katkar et al. (Katkar hereinafter) (US 11,031,285).
Regarding Claims 1-5, 7-10, and 12:
Katkar (see FIGs. 3A, 4B) teaches
{1} a semiconductor structure comprising: a first bond pad 106 embedded in a first dielectric layer in a first substrate 102; a second bond pad 108 embedded in a second dielectric layer in a second substrate 104; and an oxygen-containing inter-layer bonding the first substrate with the second substrate, wherein at least a first portion 302 of the oxygen-containing inter-layer is vertically directly between the first bond pad in the first substrate and the second dielectric layer in the second substrate and horizontally directly between the second bond pad and a third portion of the oxygen-containing inter-layer, the first portion of the oxygen-containing inter-layer including a first alloy element such that it is materially different from the third portion of the oxygen-containing inter-layer;
{2} a second portion 302 of the oxygen-containing inter-layer is vertically directly between the first dielectric layer in the first substrate and the second bond pad in the second substrate and horizontally directly between the first bond pad and a fourth portion of the oxygen-containing inter-layer, the second portion of the oxygen-containing inter- layer being materially different from the fourth portion of the oxygen-containing inter- layer to include including a second alloy element;
{3} the first and the second bond pad are made of copper to be a first and a second copper pad respectively, and the first copper pad is directly bonded to the second copper pad;
{4} the first and the second alloy element are an alloy element selected from a group consisting of manganese, aluminum, zirconium, titanium, tin, or a combination thereof;
{5} the first and the second portion of the oxygen-containing inter-layer include manganese-oxide, aluminum-oxide, zirconium-oxide, titanium-oxide, or tin-oxide;
{7} the third portion of the oxygen-containing inter-layer is vertically directly between the first dielectric layer in the first substrate and the second dielectric layer in the second substrate;
{8} a semiconductor structure comprising: a first copper pad 106 embedded in a first dielectric layer 102; a second copper pad 108 embedded in a second dielectric layer 104; and an oxygen-containing inter-layer, wherein a portion 302 of the oxygen-containing inter-layer is directly between the first copper pad and the second dielectric layer and horizontally directly adjacent to another portion of the oxygen-containing inter-layer that is directly between the first dielectric layer and the second dielectric layer, the portion of the oxygen-containing inter-layer is materially different from the another portion of the oxygen-containing inter-layer and includes a first alloy element of manganese, aluminum, zirconium, titanium, tin, or a combination thereof; {9} the portion of the oxygen-containing inter-layer is a first portion 302 of the oxygen-containing inter-layer, further comprising a second portion 302 of the oxygen-containing inter-layer, the second portion of the oxygen-containing inter-layer is directly between the first dielectric layer and the second copper pad, is materially different from the another portion of the oxygen- containing inter-layer, and includes a second alloy element;
{10} the another portion of the oxygen-containing inter-layer that is directly between the first dielectric layer and the second dielectric layer horizontally surrounds a portion of the first copper pad and a portion of the second copper pad; and
{12} a majority of the first copper pad is bonded directly to the second copper pad.
Katkar (see col.3/ll.9-12, col.4/ll.57-64, col.5/ll.20-47, and col.7/ll.11-28) teaches “the use of a barrier interface disposed generally between the conductive material and the dielectric that can inhibit the diffusion of the conductive layer into surrounding dielectric material”; “The substrates 102 and 104 are comprised of an insulating material or dielectric (e.g., silicon oxide, or the like), at least at the bonding surface of each substrate 102 and 104 … can represent the top insulating layer of a microelectronic component comprised of a base layer (of active semiconductor …) topped with one or more metallization layers within associated insulating layers”; “The surfaces of the substrates 102 and 104 are bonded via direct bonding … dielectric to dielectric at room temperature without the use of adhesive. Then with high temperature annealing (<350 C), the contact pads 106 and 108 expand and form a metal-to-metal bond creating an electrical connection … the conductive material (e.g., copper or a copper alloy, etc.) of one or both of the conductive structures 106 and 108 may diffuse into the insulating material or dielectric of the substrates 104 and 102 due to this contact”; “the barrier interface(s) 302 comprise one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, diamond, boron doped glass or oxide, aluminum oxide, or a like diffusion resistant material … nickel, a nickel alloy, or one or more other conductive materials in various combinations”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. (Katkar hereinafter) (US 11,031,285) as applied to claim 1 or 8 above, and further in view of Hagimoto et al. (Hagimoto hereinafter) (US 2016/0141267).
Regarding Claims 6 and 11:
Katkar does not explicitly teach {6} the third portion of the oxygen-containing inter-layer is a layer of silicon-oxynitride, or a bilayer of silicon-nitride and oxygen doped silicon-carbide; and {11} the another portion of the oxygen-containing inter-layer is a layer of silicon-oxynitride, or a bilayer of silicon-nitride and oxygen doped silicon-carbide.
Hagimoto (see ¶ [0052]) teaches “The layer formed on the outermost surface of the interlayer insulating layer 32 is composed, for example, from an oxide, such as SiO, HfO, GeO, GaO or SiON, or from a nitride insulating layer and a metallic oxide”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Katkar to further include the teaching of Hagimoto to use other well-known insulating material, such as SiON as the outermost surface of the interlayer insulating layer in semiconductor art.
Claims 13 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. (Katkar hereinafter) (US 11,031,285) in view of Amanapu et al (Amanapu hereinafter) (US 10,204,829).
Regarding Claims 13 and 17-20:
Katkar (see FIGs. 3A and 4B) teaches
{13} a method comprising: providing a first and a second substrate; forming a first oxygen-containing inter-layer 102/302 on the first substrate and forming a second oxygen-containing inter-layer 104/302 on the second substrate; forming a first copper pad 106 with a first alloy element in the first substrate and forming a second copper pad 108 with a second alloy element in the second substrate; attaching the first substate to the second substrate by bonding the first copper pad with the second copper pad and bonding the first oxygen-containing inter-layer with the second oxygen-containing inter-layer, wherein at least a portion of the first copper pad is bonded directly with the second oxygen-containing inter-layer in a first region 302 of the second oxygen-containing inter-layer;
{17} the first and the second alloy element are manganese, aluminum, zirconium, titanium, tin, or a combination thereof and are materially different from each other;
{18} forming the first copper pad with the first alloy element comprises forming an alloy seed layer containing the first alloy element in an opening in the first substrate; and
{20} the first region is between the first copper pad and the second substrate surrounding the second copper pad wherein the second copper pad partially protrudes from the second substrate, and the second region is between the first substrate surrounding the first copper pad and the second copper pad wherein the first copper pad partially protrudes from the first substrate.
Katkar (see col.5/ll.43-47) teaches “the conductive material (e.g., copper or copper alloy, etc.) of one or both of the conductive structures 106 and 108 may diffuse into the insulating material or dielectric of substrates 104 and 102 dues to this contact”;
However, Katkar does not explicitly teach {13} annealing the first and the second substrate to segregate the first alloy element from the first copper pad into the first region, causing the first region to be materially different from another region of the second oxygen-containing inter-layer that is not directly bonded with the first copper pad; {18} performing an electroplating of copper on top of the alloy seed layer; and {19} at least a portion of the second copper pad is bonded directly with the first oxygen-containing inter-layer in a second region, and at least some of the second alloy element is segregated from the second copper pad into the second region.
Amanapu (see col.2/ll.42-48 and col.7/ll.42-43) teaches “the seed layer comprises a copper-manganese alloy; depositing a layer of copper material to fill the opening with copper material; and performing a thermal anneal treatment to cause manganese atoms of the seed layer to diffuse into the sidewall surfaces of the opening in the dielectric layer to form an embedded barrier layer which is embedded within the sidewall surfaces” and “the copper layer is deposited using a web deposition technique such as electroplating … the thermal anneal process is performed in a furnace at a target temperature range and for a target period of time, which is sufficient to enable diffusion of the manganese atoms of the seed layer 170 into the vertical sidewalls of the dielectric layer 140 to create the self-formed diffusion barrier layers 190. The remaining material (e.g., copper) of the seed layer 170 becomes part of the metallic material 180 (e.g., copper) that fills the opening 140-1 to form a metallic interconnect structure”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Katkar to include the teaching of Amanapu to replace the deposited barrier interfaces 302 with self-formed diffusion barrier interfaces by adding an alloy seed layer between the copper pad and the dielectric layer so that one of the metal in the alloy seed layer, migrating into the dielectric layer during thermal anneal treatment and to form the copper layer by electroplating which is well-known manufacturing technique for copper.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. (Katkar hereinafter) (US 11,031,285) in view of Amanapu et al (Amanapu hereinafter) (US 10,204,829) as applied to claim 13 above, and further in view of Gondcharton et al. (Gondcharton hereinafter) (US 10,115,698).
Regarding Claims 14 and 15:
Katkar (see col.5/ll.20-26, col.8/l.61-col.9/l.7) teaches “the surface of the substrate 102 and 104 are bonded via direct bonding … dielectric to dielectric at room temperature without the use of adhesive … with high temperature annealing (<350 C), the contact pads 106 and 108 expand and form a metal-to-metal bond creating an electrical connection”, “the bonding surfaces may be heat treated at around 100-150° C. for 2 to 4 hours to form a strong bond between the substrates 102 and 102. The pads 204 and 206 may then be annealed during a second treatment using a pulse anneal technique at approximately 250-400° C. for 10 seconds to less than 300 second … the adjusted heating/annealing times are effective to reduce or eliminate the mismatch stress or load of the bonded microelectronic assembly 300”.
Gondcharton teaches during the bonding process of two substrates with metal bonding layers can be performed at a temperature typically between 20-50° C. at atmospheric pressure.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Katkar in the method of Amanapu to further include the teaching of Gondcharton to bond two substrates with metal contact at a temperature between 20-50° C in a very short duration as long as they contact each other and then to anneal them at higher temperature for longer so that the Cu electrodes are joined and the non-Cu metal element can be partially or fully diffused into dielectric layer to prevent Cu diffusion in order to improve the reliability of the devices and the specific range of temperature and duration of the annealing process depends on the materials used for the non-Cu metal element and the dielectric layer, the thickness of the CuMn layer, and the pressure used.
The differences in the temperature range and duration used to bond two structures together and the temperature range and duration used in a thermal annealing process after the bonding will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such temperature ranges and durations are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the instant invention, it would have been obvious to one of ordinary skill in the art to bond two structures at low temperature in the range of about 25-50° C for a duration of about 10 seconds to 2 minutes as long as they contact each other and then to anneal the structures at a temperature of 350-400° C for 1 minute to 2 hours so that the Cu electrodes are joined and the diffusion barriers are formed to prevent the Cu migration to the dielectric layer in order to improve the reliability of the devices.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934, 1936s (Fed. Cir. 1990).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. (Katkar hereinafter) (US 11,031,285) in view of Amanapu et al (Amanapu hereinafter) (US 10,204,829) as applied to claim 13 above, and further in view of Hagimoto et al. (Hagimoto hereinafter) (US 2016/0141267).
Regarding Claim 16:
Katkar in the method of Amanapu does not explicitly teach the first and the second oxygen-containing inter-layers are a layer of silicon-oxynitride or a bilayer of silicon-nitride and oxygen doped silicon-carbide.
Hagimoto (see ¶ [0052]) teaches “The layer formed on the outermost surface of the interlayer insulating layer 32 is composed, for example, from an oxide, such as SiO, HfO, GeO, GaO or SiON, or from a nitride insulating layer and a metallic oxide”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Katkar in the method of Amanapu to further include the teaching of Hagimoto to use other well-known insulating material, such as SiON as the outermost surface of the interlayer insulating layer in semiconductor art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights