E DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, Claims 1-11 and 17-20, without traverse, is acknowledged. Claims 12-16 are withdrawn from consideration
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (US 2015/0333069), (hereinafter, KIM).
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RE Claim 1, KIM discloses in FIGS. 1-23 a semiconductor memory device and a method of making the same. KIM discloses a semiconductor device comprising:
an active region 102a/102b between portions of a device isolation layer 104 on a substrate 100;
a self-aligned pad layer 116a on a first region of the active region 102, referring to FIG. 2. Examiner notes that “self-aligned” is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966;
a bit tine 112 that is electrically connected to a second region of the active region 102a/102b, referring to FIG. 2; and
a contact structure 116b “upper contact” on a side surface of the bit line 112 and electrically connected to the self-aligned pad layer 116a,
wherein the self-aligned pad layer 116a comprises a pad protrusion that extends along an upper portion of a side surface of the first region of the active region 102a/102b, referring to the annotated FIG. 2 above, and
wherein a side of the self-aligned pad layer 116a is in contact with the device isolation layer 104.
RE Claim 2, KIM discloses a semiconductor device, wherein a width of an upper portion of the self-aligned pad layer 116a is less than a width of a lower portion of the self- aligned pad layer 116a, referring to FIG. 2.
RE Claim 3, KIM discloses a semiconductor device, wherein a lower surface of the pad protrusion of the self-aligned pad layer 116a is lower than an upper surface of the device isolation layer 104 with respect to the substrate 100, referring to FIG. 2.
RE Claim 4, KIM discloses a semiconductor device, wherein the self-aligned pad layer 116a comprises polysilicon [0031].
RE Claim 5, KIM discloses a semiconductor device, wherein in plan view, the pad protrusion overlaps an upper surface of the first region of the active region 102a/102b with a substantially uniform thickness, referring to FIG. 2.
RE Claim 6, KIM discloses a semiconductor device, wherein in plan view, the active region 102 has a rectangular shape having a major axis and a minor axis, referring to FIGS. 1 and 2, examiner notes that the minor axis of the active region 102a/102b width is shown in FIG. 2,
wherein in plan view, the active region 102a/102b has a first surface and a second surface parallel to the major axis, referring to FIGS. 1 and 2, and
wherein the self-aligned pad layer 116a has a third surface parallel to the first surface of the active region and a fourth surface parallel to the second surface of the active region 102a/102b, referring to FIGS. 1 and 2. Examiner notes that the first, second, third and fourth surfaces of the active region and self-aligned pad are represented by the edge boundaries of both regions as shown in FIGS. 1 and 2 [0027].
RE Claim 7, KIM discloses a semiconductor device, wherein the active region 102a/102b has a rectangular shape having a major axis and a minor axis, referring to FIGS. 1 and 2, and
wherein a width of the self-aligned pad layer 116a is greater than a width of the active region 102a/102b in a direction of the minor axis, referring to FIG. 2.
RE Claim 8, KIM discloses a semiconductor device, wherein in plan view, the self- aligned pad layer 116a comprises a first pattern portion on a first end of the active region and a second pattern portion on a second end opposite to the first end of the active region 102a/102b, referring to FIG. 2. Since the self-aligned pad 116a resides on both sides of the bit line 112, the claimed limitations are met.
RE Claim 9, KIM discloses a semiconductor device, further comprising:
a word line structure 106/108/222/224/226 “buried gates” [0034] on a side surface of the active region102/102a/102b and extending into the device isolation layer 104, referring to FIGS. 1, 2 and 10,
wherein the word line structure comprises a gate dielectric layer 108/222, a word line 106/224 “buried gate” on the gate dielectric layer 108/222, and a gate capping layer 226 on the word line 106/224, and
wherein a side surface of the word line structure 106/108/222/224/226 is in contact with the self- aligned pad layer 116a/232, referring to FIGS. 2 and 13.
RE Claim 10, KIM discloses a semiconductor device, wherein an upper surface of the gate capping layer 226 is on substantially at a same level as an upper surface of the self-aligned pad layer 116a/232with respect to the substrate 100, referring to FIGS. 2 and 13.
RE Claim 11, KIM discloses a semiconductor device, further comprising:
a buffer insulating layer 244 on the device isolation layer 216 and the self-aligned pad layer 234, referring to FIG. 18, a step of the fabrication process;
a bit line contact pattern 252 electrically connected to the bit line 236 and in a bit line contact hole that penetrates the buffer insulating layer 244, referring to FIGS. 20 and 22;
a spacer structure between 238 the bit line 236 and the contact structure 252;
an isolation insulating pattern 236b “hard mask layer” that penetrates the contact structure 252; and
an information storage structure “storage node on the contact structure 252 and electrically connected to the contact structure 252 [0064]. Examiner notes that KIM discloses that a storage node will be formed on the contact structure in a later processing step [0064], however the storage node which is equivalent to the information storage structure is not shown in the figures, hence the claimed limitations are met.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(1)/ 102(a)(2) as being anticipated by KIM et al. (US 2022/0384449), (hereinafter, KIM).
RE Claim 17, KIM discloses a semiconductor memory device with specific isolation pattern. KIM discloses a semiconductor device semiconductor device comprising:
active regions ACT between portions of a device isolation layer 302 on a substrate 301, referring to FIGS. 1B and 3A;
self-aligned pad XP layers on the active regions ACT. Examiner notes that “self-aligned” is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966; and
bit lines BL that are electrically connected to the active regions ACT, respectively, wherein the device isolation layer 302 comprises a first portion between adjacent ones of the active regions ACT and a second portion between adjacent ones of the self-aligned pad layers XP. Examiner notes that the second portion is adjacent to a protruding portion of the self-aligned pad layers XP, referring to FIG.1B and 3A, and
wherein the device isolation layer 302 includes a bent portion in a region in which the first portion and the second portion are connected to each other. Examiner notes that the a protruding portion of the self-aligned pad layer XP is at the intersection of the first and second portions of the isolation layer 302 and is bent portion, referring to FIG. 3A, hence meeting the claimed limitation.
RE Claim 18, KIM discloses a semiconductor device, wherein the second portion of the device isolation layer 302 is in contact with side surfaces of the self-aligned pad layers XP, referring to FIG. 3A.
RE Claim 19, KIM discloses a semiconductor device, wherein the second portion of the device isolation layer 302 is higher than an upper surface of a respective one of the active regions ACT with respect to the substrate 301, referring to FIGS.1B and 3A.
RE Claim 20, KIM discloses a semiconductor device, wherein a width of a lower portion of the first portion is less than a width of an upper portion of the second portion, referring to FIG. 3A.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached at (571)272-8936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898