Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chung et al. (US Pat. Pub. 2015/0364432).
Regarding claim 19, Chung teaches a method for manufacturing a semiconductor device, the method comprising:
preparing a semiconductor wafer including a plurality of firsts semiconductor chips partitioned by a scribe lane, the first semiconductor chip including a first semiconductor substrate, a first semiconductor element layer formed on a lower surface of the first semiconductor substrate and a first through silicon via connected to a wiring structure disposed in the first semiconductor element layer by passing through at least a portion of the first semiconductor substrate, wherein the first through silicon via includes a lower surface disposed in the first semiconductor substrate and an upper surface opposite to the lower end [figs. 14a and 14b, chips 1100 partitioned by scribe lanes L3, first substrate 100, element layer 110, through silicon via 120 with a lower surface in substrate 100];
removing a trim region of the first semiconductor substrate along an edge portion of the semiconductor wafer to form a remaining edge region [fig.4a and 4b, the substrate 100 has been trimmed along and edge portion 110a];
attaching the semiconductor wafer to a carrier substrate, wherein the remaining edge region is in contact with the carrier substrate [fig. 6b, carrier 500, substrate 100 is in contact with 500 through layers 400 and 420]; and
forming an edge protection layer along the remaining edge region [fig. 5b, 400],
wherein removing the trim region of the first semiconductor substrate along the edge portion of the semiconductor wafer is performed by any one of
removing the trim region to a depth deeper than the first through silicon via from a lower surface of the first semiconductor substrate toward an upper surface of the first semiconductor substrate along the edge portion of the semiconductor wafer,
removing the trim region at a predetermined angle from sides of the first semiconductor substrate toward the lower surface of the first semiconductor substrate along the edge portion of the semiconductor wafer, wherein the sides are lower than the lower end of the first through silicon via, and
removing the trim region in the form of a groove recessed from the lower surface of the first semiconductor substrate toward the upper surface of the first semiconductor substrate along the edge portion of the semiconductor wafer [fig. 6b shows the removing step has removed the trim region in the form of a groove recessed from the lower surface of the firs semiconductor substrate towards the upper surface of the first semiconductor substrate].
Regarding claim 20, Chung disclose the method of claim 19, wherein the edge protection layer has a ring shape along the edge portion of the semiconductor wafer on the carrier substrate or disposed in the form of arcs spaced apart from each other at a constant interval [fig. 4a, the trim region at the edge is in a ring shape, fig. 5a, the edge protection layer 400 is also in a ring shape along the edge 100a].
Allowable Subject Matter
Claims 1-18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art fails to disclose or suggest the method as claimed. Specifically, the prior art fails to teach forming a second final passivation layer to expose the upper surface of the first through silicon via and forming a plurality of first upper connection pads on the second final passivation layer, wherein the plurality of first upper connection pads are electrically connected to the first through silicon via.
Regarding claim 9, the prior art fails to disclose or suggest the method as claimed. Specifically, the prior art fails to teach forming a second final passivation layer to expose the upper surface of the first through via and forming a plurality of first upper connection pads on the second final passivation layer, where the plurality of first upper connection pads are electrically connected to the first through silicon via on the second final passivation layer.
Conclusion
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/JOHN M PARKER/Examiner, Art Unit 2899