DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 and 17-22 in the reply filed on 4/1/26 is acknowledged.
Also, the applicant fails to respond to the species restriction of restriction dated 2/2/26, for examination purposes, it is assumed that the elected claims 1-16 and 17-22 read on the first embodiment of figs. 1A-1B and 2A-2B.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 5, 6, 9, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meyer et al. (US pub 20180286799).
With respect to claim 1, Meyer et al. teach a microelectronic device package, comprising (see figs. 1-5, particularly fig. 1F and associated text):
a multilayer package substrate 110 comprising trace level conductors 130 spaced by dielectric material, 1221, 1222 the multilayer package substrate having a device side surface (top) and an opposing board side surface (bottom), and having a recess (area where 176 occupies) extending from the device side surface and exposing selected ones of the trace level conductors beneath the device side surface of the multilayer package substrate;
a semiconductor die 140 mounted to the device side surface of the multilayer package substrate and coupled to the trace level conductors;
a passive component 176 mounted to the selected ones of the trace level conductors exposed in the recess in the multilayer package substrate; and
mold compound 188 covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.
With respect to claim 3, Meyer et al. teach the passive component comprises a two-terminal device 172,174. See fig. 1F and associated text.
With respect to claim 4, Meyer et al. teach the passive component comprises a capacitor, an inductor, a coil, a resistor, a diode or a sensor. See para 0017.
With respect to claim 5, Meyer et al. teach the passive component comprises a capacitor. See para 0017.
With respect to claim 6, Meyer et al. teach the capacitor has a capacitor thickness that is greater than a thickness of the semiconductor die. See fig. 1F and associated text.
With respect to claim 9, Meyer et al. teach the capacitor has a capacitor thickness that is greater than a thickness of the mold compound over the device side surface of the multilayer package substrate. See fig. 1F and associated text.
With respect to claim 10, Meyer et al. teach the multilayer package substrate comprises the trace level conductors 126 spaced from one another by the dielectric material, and further comprises connection level conductors 124 between layers of the trace level conductors, the connection level conductors extending through the dielectric material to couple the trace level conductors. See fig. 1F and associated text.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 7, 8, 11, 12, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meyer et al. (US pub 20180286799).
With respect to claim 2, Meyer et al. teach the semiconductor die comprises of power device (see para 0035) but fail to teach the power device is power FET device.
However, use of power FET device is well-known in semiconductor art.
With respect to claim 7, Meyer et al. fail to teach the range for the thickness for capacitor.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the thickness for capacitor through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that claimed range is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05.
With respect to claim 8, Meyer et al. fail to teach the ranges for the length and width for capacitor.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the length and width for capacitor through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that claimed ranges are critical or produce any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05.
With respect to claim 11, Meyer et al. fail teach the dielectric material comprises Ajinomoto build-up film (ABF).
However, the use of Ajinomoto build-up film (ABF) as dielectric material is well-known in semiconductor art.
With respect to claim 12, Meyer et al. fail teach the dielectric material comprises resin epoxy.
However, the use of resin epoxy as dielectric material is well-known in semiconductor art.
With respect to claim 13, Meyer et al. teach the package substrate comprises an embedded trace substrate but fail teach the dielectric material comprises prepreg material
However, the use of prepreg material as dielectric material is well-known in semiconductor art.
With respect to claim 16, Meyer et al. fail teach the microelectronic device package further comprises a quad flat no-lead (QFN) package.
However, the use of quad flat no-lead (QFN) package is well-known in semiconductor art.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meyer et al. (US pub 20180286799).
With respect to claim 17, Meyer et al. teach a microelectronic device package, comprising (see figs. 1-5, particularly figs. 2C-2E and associated text):
a package substrate 200 having a device side surface (top) and an opposing board side surface (bottom), and having a portion configured for mounting a passive component 176 on the device side surface;
a semiconductor die 140 mounted to the device side surface of the package substrate;
mold compound 110 covering the device side surface of the package substrate and covering the semiconductor die;
a recess 132 extending into the mold compound exposing the portion of the package substrate configured for mounting the passive component on the device side surface; and
a passive component 176 mounted to the portion of the package substrate in the recess in the mold compound, the passive component coupled to the semiconductor die.
With respect to claim 18, Meyer et al. teach solder fill material deposited in the recess in the mold compound and surrounding the passive component. See fig. 2C-2E and associated text.
With respect to claim 18, Meyer et al. teach solder fill material deposited in the recess in the mold compound and surrounding the passive component. See fig. 2C-2E and associated text.
With respect to claim 19, Meyer et al. teach the passive component has a thickness greater than the thickness of the mold compound. See fig. 2C-2E and associated text.
With respect to claim 20, Meyer et al. teach the passive component comprises a capacitor, an inductor, a coil, a resistor, a diode or a sensor. See para 0017.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meyer et al. (US pub 20180286799).
With respect to claim 8, Meyer et al. fail to teach the ranges for the thickness, the length and width for capacitor.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the thickness, the length and width for capacitor through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that claimed ranges are critical or produce any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05.
Allowable Subject Matter
Claims 14-16 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having a package having a passive device partly embedded in a multi-layer package substrate and a mold covering a semiconductor device and the passive device as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897
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