DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/11/2026 has been entered.
Status of Application
In response to Office action mailed 12/31/2025, Applicants amended claim 1, 15 and 21 and cancelled claims 11, 18-20, 23-24, 26 and 28 in the response filed 02/11/2026.
Claim(s) 1-10, 12-17, 21-22, 25 and 27 are pending examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10, 12-17, 21-22, 25 and 27 have been considered but are moot because the arguments do not apply to the new combination of references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (PG Pub 2020/0043853; hereinafter Kim), Zhai et al. (PG Pub 2016/0148904; hereinafter Zhai) and Tsou et al. (PG Pub 2021/0375768).
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Regarding claim 1, refer to the Examiner’s modified mark-up of Fig. 3 provided above, Kim teaches a semiconductor package 1, comprising:
a package substrate 100;
a first chip structure (annotated “chip struct-1” in Fig. 1a above) mounted on the package substrate (see Fig.1 a);
a first semiconductor chip 310 mounted on the first chip structure (see Fig.1 a); and
wherein the first chip structure comprises:
a second interposer 230 (para [0072]);
a second molding layer 252 disposed on a lateral surface of the second semiconductor chip;
a first redistribution layer 260 disposed on the second semiconductor chip and the second molding layer (see Fig. 1a), the first redistribution layer comprising a substrate wiring layer (212,214,216 LY11, LY12, LY13) which includes a substrate dielectric pattern (LY11, LY12, LY13) and a substrate wiring pattern (212, 214, 216) in the substrate dielectric pattern (see Fig.1 a); and
a first through electrode 220 disposed on a side (e.g. left and right side; see Fig. 1a) of the second semiconductor chip and connected to the first redistribution layer (see Fig.1 a),
Although, Kim teaches the first chip structure comprises a second chip structure, he does not explicitly teach that second chip structure is a “second semiconductor chip;” or “a first molding layer that surrounds the first chip structure and the first semiconductor chip on the package substrate.”
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In the same field of endeavor, refer to Fig. 2j-provided above, Zhai teaches a semiconductor package comprising: a package substrate 212; a first chip structure 206,208 mounted on the package substrate (see Fig. 2j); a first semiconductor chip 108 mounted on the first chip structure (see Fig.2j); and
wherein the first chip structure comprises: a second semiconductor chip structure 208; and a molding layer 260 (para [0043]) that surrounds the first chip structure and the first semiconductor chip on the package substrate (see Fig. 2j)
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the molding layer surround the first chip structure and second semiconductor die of Kim, as taught by Zhai, to provide a more robust package; while allowing inter-communication between a plurality of chips.
Note: by incorporating the first molding layer of Zhai over the first chip structure and second chip of Kim (Refer to the combined Fig. 3 above), the claimed limitation of “a portion of the first molding layer is disposed directly on an uppermost surface of the first redistribution layer” is taught.
Although, the combined invention of Kim and Zhai teach a second chip structure 9e.g. an interposer/bridge, they do not explicitly refer to this structure as a die. However, in the same field of endeavor, Tsou teaches a bridge die is an interposer structure (para [0029]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second semiconductor chip of the combined invention function as a bridge die, as taught by Tsou, to provide electrical/signal commutations between the upper chips, as taught by Tsou.
Regarding claim 3, refer to the combined representation of Fig. 3 provided above, in the combination of Kim, Zhai and Tsou, Kim teaches when viewed in a plan view, the second molding layer 252 surrounds the second semiconductor chip 230, and the first through electrode 220 is provided in plural (see Fig. 3), and the plurality of first through electrodes are arranged to surround the second semiconductor chip (see Fig. 3).
Regarding claim 4, refer to the combined representation of Fig. 3 provided above, in the combination of Kim, Zhai and Tsou, Kim teaches the first semiconductor chip 310 is mounted on the first redistribution layer 260 through a third connection terminal (annotated “connect” in Fig. 3 above) between the first semiconductor chip and the first redistribution layer (see Fig. 3 above).
Regarding claim 5, refer to the combined representation of Fig. 3 provided above, in the combination of Kim, Zhai and Tsou, Kim teaches at least a portion of the first semiconductor chip 310 vertically overlaps the second molding layer 252 (see Fig. 3).
Regarding claim 13, refer to the combined representation of Fig. 3 provided above, in the combination of Kim, Zhai and Tsou, Kim teaches the first through electrode 220 vertically penetrates the second molding layer 252, the first through electrode being coupled to the first redistribution layer 260 and exposed on a bottom surface of the second molding layer (see Fig. 3).
Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Zhai and Tsou, as applied to claim 1 above, and further in view of Zhai et al. (PG Pub 2016/0300813; hereinafter Zhai-2).
Regarding claim 6, refer to the combined representation of Fig. 3 provided above, in the combination of Kim, Zhai and Tsou, Kim teaches the first chip structure (“chip struct-1”). Kim does not teach “a third semiconductor chip horizontally spaced apart from the second semiconductor chip, the second molding layer surrounds the first semiconductor chip and the third semiconductor chip, and the first redistribution layer is on the second semiconductor chip, the third semiconductor chip, and the second molding layer.”
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In the same field of endeavor, refer to Fig. 14 provided above, Zhai-2 teaches a semiconductor package (para [0025-0051]) comprising: a third semiconductor chip 150-R (para [0042]) horizontally spaced apart from a second semiconductor chip 150-L (para [0042]), a second molding layer 170 (para [0045]) surrounds a first semiconductor chip and the third semiconductor chip, and a first redistribution layer 130 (para [0038]) is on the second semiconductor chip, the third semiconductor chip, and the second molding layer (see Fig. 14).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first chip structure further include a third semiconductor chip horizontally spaced apart from the second semiconductor chip, as taught by Zhai-2, to create a more robust package.
Note: Zhai teaches the placements of die-1, die-2, die-3 and die-4 with respect to the first chip structure. By placing a third semiconductor die adjacent to the second semiconductor die (within the first chip structure) and a fourth semiconductor die adjacent to the first semiconductor die, "the second molding layer surrounds the first semiconductor chip and the third semiconductor chip, and the first redistribution layer is on the second semiconductor chip, the third semiconductor chip, and the second molding layer" would be taught.
Regarding claim 7, refer to the combined representation of Fig. 3 provided above, the combination of Kim, Zhai, Tsou and Zhai-2 teach a fourth semiconductor chip 320-Kim on the first chip structure (“chip struct-1” of Kim) and horizontally spaced apart from the first semiconductor chip 310-Kim, the fourth semiconductor chip being mounted on a first redistribution layer 260-Kim of the first chip structure (see combined Fig. 3), wherein the first semiconductor chip (110-L of Zhai-2 = 310 of Kim) is on the second semiconductor chip (150-L of Zhai-2), and wherein the fourth semiconductor chip (110-R of Zhai-2) is on the third semiconductor chip (150-R of Zhai-2)(see Fig. 14 of Zhai-2).
Regarding claim 8, refer to the combined representation of Fig. 3 provided above, the combination of Kim, Zhai, Tsou and Zhai-2 teach two semiconductor chips (e.g. a first and a fourth) mounted on a first redistribution layer of the first chip structure on the second molding layer, they do not explicitly teach the inclusion of additional chips (e.g. fifth, sixth, etc...).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the number of semiconductor chips to be between the first semiconductor chip and the fourth semiconductor chip on the first chip structure, those semiconductor chips being mounted on the first redistribution layer of the first chip structure and on the second molding layer, since it has been held that the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). It is the Examiner's position that no new and unexpected result is produced, therefore the modification of duplicating parts is not a patentable feature for the invention as claimed. As a result, requiring a rationale for modifying a reference is moot because the modification is, under Harza, not a patentable feature.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Zhai and Tsou, as applied to claim 1 above, and further in view of Chen et al. (PG Pub 20180122764; hereinafter Chen).
Regarding claim 9, refer to the combined representation of Fig. 3 provided above, the combination of Kim, Zhai and Tsou, Kim teaches a first chip structure, he does not teach "a second chip structure spaced apart from the first chip structure on the package substrate, the second chip structure being mounted on the package substrate; and a third semiconductor chip mounted on the second chip structure, wherein the first molding layer surrounds the first chip structure, the first semiconductor chip, the second chip structure, and the third semiconductor chip, wherein the second chip structure comprises: a fourth semiconductor chip; a third molding layer on a lateral surface of the fourth semiconductor chip; a second redistribution layer on the fourth semiconductor chip and the third molding layer; and a second through electrode that vertically penetrates the third molding layer and is connected to the second redistribution layer."
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In the same field of endeavor. refer to Fig. 1I, Chen teaches a chip package structure (para [0015- 0079]) comprising: a second chip structure 200-right (para [0041]) spaced apart from a first chip structure 200-left (para [0041]) on a package substrate 230 (para [0044]), the second chip structure being mounted on the package substrate (see Fig. 1I); and a third semiconductor chip 130 (chip-3) mounted on the second chip structure (see Fig. 1I), wherein a first molding layer 240 surrounds the first chip structure, a first semiconductor chip 130 ("chip-1"), the second chip structure, and the third semiconductor chip (see Fig. 1I), wherein the second chip structure comprises: a fourth semiconductor chip 170 (chip-4); a third molding layer 180 ("mold-3") on a lateral surface of the fourth semiconductor chip (see Fig. 1I); a second redistribution layer ("RDL-2") on the fourth semiconductor chip and the third molding layer (see Fig. 1I); and a second through electrode 160 (elec-2) that vertically penetrates the third molding layer and is connected to the second redistribution layer (see Fig. 1I).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second chip structure, as taught by Chen, into the package of Yu, to create a more robust package.
Claim(s) 15-16 and 21-22, 25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (PG Pub 2020/0043853; hereinafter Kim) and Zhai et al. (PG Pub 2016/0148904; hereinafter Zhai).
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Regarding claim 15, refer to the Examiner’s modified mark-up of Fig. 3 provided above, Kim teaches a semiconductor package 1, comprising:
a package substrate 100;
a first semiconductor chip 230 mounted on the package substrate (see Fig. 3);
a first molding layer 252 that surrounds a lateral surface of the first semiconductor chip (see Fig. 3);
a first through electrode 220 that vertically penetrates the first molding layer and is mounted on the package substrate through a first connection terminal (metal wiring of the lower RDL) on a bottom surface of the first molding layer (see Fig. 3);
a first redistribution layer 260 disposed on the first semiconductor chip and the first molding layer (see Fig. 3), the first redistribution layer being electrically coupled to the first through electrode (thru the metal wiring within 260);
a second semiconductor chip 310 flip-chip mounted on the first redistribution layer in a stacking direction (see Fig. 3).
Kim does not teach “a second molding layer disposed on the package substrate, the second molding layer covering the first molding layer, the first redistribution layer, and the second semiconductor chip, wherein the second molding layer overlaps the second semiconductor chip in the stacking direction.”
Kim does not teach “the second semiconductor chip is flip chip mounted on the package substrate through a first connection terminal between the package substrate and the second semiconductor chip.”
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In the same field of endeavor, refer to Fig. 2j-provided above, Zhai teaches a semiconductor package comprising: a second semiconductor chip 108 is flip-chip mounted on a package substrate 212 through a first connection terminal 106 between the package substrate and the second semiconductor chip (see Fig. 2j).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mount the second semiconductor chip to the package substrate through a first connection terminal, as taught by Zhai, to provide electrical/signal interconnection between the package substrate and the second semiconductor chip.
Regarding claim 16, refer to the combined representation of Fig. 3 provided above, the combination of Kim and Zhai teach at least a portion of the second semiconductor chip 310 vertically overlaps the first molding layer 252 (see Fig. 3).
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Regarding claim 21, refer to the Examiner’s modified mark-up of Fig. 3 provided above, Kim teaches a semiconductor package 1, comprising:
a package substrate 100;
a first chip structure (annotated “chip struct-1” in Fig. 1a above) on the package substrate (see Fig. 3); and
a first semiconductor chip 310 on the first chip structure (see Fig.1 a),
wherein the first chip structure comprises: a second semiconductor chip 230; a vertical connection terminal 220 on a side of the second semiconductor chip (e.g. left or right); and a first redistribution layer 260 on the second semiconductor chip and the vertical connection terminal (see Fig. 3), the first redistribution layer being electrically connected to the vertical connection terminal (see Fig. 3), and on which is mounted the first semiconductor chip (see Fig. 3),
wherein the vertical connection terminal is mounted on the package substrate through a second connection terminal (top metal wiring layer of 210) between the package substrate and the vertical connection terminal (see Fig. 3), and
wherein the first redistribution layer is wider than the first semiconductor chip (see Fig. 3) and comprises a substrate wiring layer 262,264,266 which includes a substrate dielectric pattern 266 and a substrate wiring pattern 262,264 in the substrate dielectric pattern (see Fig. 3).
Kim does not teach “the second semiconductor chip is mounted on the package substrate through a first connection terminal between the package substrate and the second semiconductor chip.”
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In the same field of endeavor, refer to Fig. 2j-provided above, Zhai teaches a semiconductor package comprising: a second semiconductor chip 208 is mounted on a package substrate 212 through a first connection terminal 206 between the package substrate and the second semiconductor chip (see Fig. 2j).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mount the second semiconductor chip to the package substrate through a first connection terminal, as taught by Zhai, to provide electrical/signal interconnection between the package substrate and the second semiconductor chip.
Regarding claim 22, refer to the combined representation of Fig. 3 provided above, the combination of Kim and Zhai teach the first chip structure (“chip struct-1”) further includes a first molding layer 252 that surrounds the second semiconductor chip 230 (see Fig. 3), the first redistribution layer 260 covers the first molding layer and the second semiconductor chip (see Fig. 3), and the vertical connection terminal 220 includes a through electrode that vertically penetrates the first molding layer, the through electrode being coupled to the first redistribution layer (see Fig. 3).
Regarding claim 25, refer to the combined representation of Fig. 3 provided above, the combination of Kim and Zhai teach the second semiconductor chip 230 is in a face-down state on the package substrate (100-Kim = 212-Zhai), and the first redistribution layer (260-Kim = 112-Zhai) is on inactive surface of the second semiconductor chip (see Fig. 2j).
Regarding claim 27, refer to the combined representation of Fig. 3 provided above, the combination of Kim and Zhai teach at least a portion of the first semiconductor chip 310 vertically overlaps the first molding layer 252.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Zhai, as applied to claim 15 above, and further in view of Zhai et al. (PG Pub 2016/0300813; hereinafter Zhai-2).
Regarding claim 17, refer to the combined representation of Fig. 3 provided above, the combination of Kim and Zhai teach the first semiconductor chip 230 flip-chip mounted on the package substrate 100; wherein the first molding layer 252 surrounds the first semiconductor chip, and wherein the first redistribution layer 260 is on the first semiconductor chip and the first molding layer (see Fig. 3).
He does not teach a third semiconductor chip horizontally spaced apart from the first semiconductor chip, and wherein the first redistribution layer is on the first semiconductor chip, the third semiconductor chip.
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In the same field of endeavor, refer to Fig. 14 provided above, Zhai-2 teaches a semiconductor package (para [0025-0051]) comprising: a third semiconductor chip 150-R (para [0042]) horizontally spaced apart from a first semiconductor chip 150-L (para [0042]), and wherein a first redistribution layer 130 is on the first semiconductor chip and the third semiconductor chip (see Fig. 14).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first chip structure further include a third semiconductor chip horizontally spaced apart from the first semiconductor chip, as taught by Zhai-2, to create a more robust package.
Note: Zhai teaches the placements of die-1, die-2, die-3 and die-4 with respect to the first chip structure. By placing a third semiconductor die adjacent to the first semiconductor die (within the first chip structure) the first molding layer would surround both the first semiconductor chip and the third semiconductor chip, would be taught.
Allowable Subject Matter
6. Claims 2, 10, 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 2, the first through electrode vertically penetrates the first molding layer and has a bottom surface exposed on a bottom surface of the first molding layer, and the first through electrode is mounted on the package substrate through a second connection terminal between the package substrate and the bottom surface of the first through electrode.
Claim 10 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 10, a fifth semiconductor chip between the first semiconductor chip and the third semiconductor chip, wherein the fifth semiconductor chip overlaps a portion of the first chip structure and a portion of the second chip structure.
Claim 12 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 12, a second chip structure mounted on the first chip structure, wherein the second chip structure comprises: a third semiconductor chip; a third molding layer on a lateral surface of the ninth semiconductor chip; a second redistribution layer on the third semiconductor chip and the third molding layer; and a second through electrode that vertically penetrates the third molding layer and is connected to the second redistribution layer, wherein the first semiconductor chip is mounted on the second chip structure and is connected to the first redistribution layer of the first chip structure through the second through electrode and the second redistribution layer of the second chip structure.
Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, a connection substrate below the first redistribution layer and coupled to the first redistribution layer, the connection substrate having an opening that penetrates the connection substrate, wherein the second semiconductor chip is in the opening of the connection substrate, wherein, in the opening, the second molding layer fills a space between the connection substrate and the second semiconductor chip, and wherein the first through electrode corresponds to a wiring pattern in the connection substrate.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817