DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Application
In response to Office action mailed 03/25/2026, Applicants amended claim 1, 15 and 21 in the response filed 06/18/2026.
Claim(s) 1-10, 12-17, 21-22, 25 and 27 are pending examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10, 12-17, 21-22, 25 and 27 have been considered but are moot because the arguments do not apply to the new combination of references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub 2021/0134730; hereinafter Yu) and Shih et al (PG Pub 2018/0102311; hereinafter Shih).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 16, Yu teaches a semiconductor package, comprising:
a package substrate 148;
a first chip structure (“chip struct-1”) mounted on the package substrate (see Fig. 16);
a first semiconductor chip 100 mounted on the first chip structure (see Fig. 16); and
a first molding layer 143 that surrounds the first chip structure and the first semiconductor chip on the package substrate (see Fig. 16), wherein the first chip structure comprises:
a second semiconductor chip 50 having an inactive top surface (para [0060]; “communication between the top dies 50 and the bottom dies 100 goes through the redistribution structure 148”);
a second molding layer 133 disposed on a lateral surface of the second semiconductor chip (see Fig. 16);
and
a first through electrode 141 disposed on a side of the second semiconductor chip and connected to the first redistribution layer (see Fig. 16),
Although, Yu teaches the first and second die are connected to one another through a layer, he does not explicitly teach the details of this layer; such that this layer is “a first redistribution layer disposed on the second semiconductor chip and the second molding layer, the first redistribution layer comprising a substrate wiring layer which includes a substrate dielectric pattern and a substrate wiring pattern in the substrate dielectric pattern; and a portion of the first molding layer is disposed directly on an uppermost surface of the first redistribution layer.”
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In the same field of endeavor, refer to Fig.14-provided above, Shih teaches a semiconductor package comprising: a first redistribution layer 900 disposed on a second semiconductor chip 101 and a second molding layer 550, the first redistribution layer comprising a substrate wiring layer 914 which includes a substrate dielectric pattern 912 and a substrate wiring pattern 918 in the substrate dielectric pattern (see Fig. 14).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the bonding layer of Yu with the redistribution layer of Shih, to provide electrical communication to the second semiconductor chip and potentially additional chips.
Note: by exchanging the bonding layer of Yu, with the redistribution layer of Shih, between the first and second semiconductor chip a portion of the first molding layer of Yu would be disposed directly on an uppermost surface of the first redistribution layer (see cited figures above).
Regarding claim 3, refer to the figures cited above, in the combination of Yu and Shih, Yu teaches when viewed in a plan view, the second molding layer 133 surrounds the second semiconductor chip 50, and the first through electrode141 is provided in plural (see Fig. 16), and the plurality of first through electrodes are arranged to surround the second semiconductor chip (see Fig. 16).
Regarding claim 4, refer to the figures cited above, in the combination of Yu and Shih teach the first semiconductor chip (100-Yu = 11-Shih) is mounted on the first redistribution layer 900-Shih through a third connection terminal 111-Shih between the first semiconductor chip and the first redistribution layer (see Fig. 14).
Regarding claim 5, refer to the figures cited above, in the combination of Yu and Shih, Yu teaches at least a portion of the first semiconductor chip 100 vertically overlaps the second molding layer 133 (see Fig. 16).
Regarding claim 13, refer to the figures cited above, the combination of Yu and Shih teach the first through electrode 141 vertically penetrates the second molding layer 133, the first through electrode being coupled to the first redistribution layer 900-Shih and exposed on a bottom surface of the second molding layer (see figures cited above).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Shih, as applied to claim 1 above, and further in view of Kim et al. (PG Pub 2020/0043853; hereinafter Kim).
Regarding claim 2, refer to the figures cited above, in the combination of Yu and Shih, Shih teaches the second semiconductor chip 101 is mounted on the package substrate (148-Yu = 700-Shih) through a first connection terminal 121-Shih between the second semiconductor chip and the package substrate (see Fig. 14), the first through electrode 141 vertically penetrates the first molding layer 143 and has a bottom surface (141-bottom) exposed on a bottom surface of the first molding layer (not covered with 143), and the first through electrode is mounted on the package substrate (see Fig. 16).
Yu does not teach the first through electrode is mounted on the package substrate through a second connection terminal between the package substrate and the bottom surface of the first through electrode.
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In the same field of endeavor, refer to Fig. 2-provided above, Kim teaches a semiconductor device comprising: a first through electrode 220 is mounted on a package substrate 100 through a second connection terminal 270 between the package substrate and the bottom surface of the first through electrode (see Fig. 2).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mount the first through electrode to the package substrate through a second connection terminal, as taught by Kim, to provide a way to communicate with external devices.
Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu and Shih, as applied to claim 1 above, and further in view of Zhai et al. (PG Pub 2016/0300813; hereinafter Zhai).
Regarding claim 6, refer to the figures cited above, in the combination of Yu and Shih, Yu teaches the first chip structure (“chip struct-1”) wherein the second molding layer surrounds the first semiconductor and the first redistribution layer 900-Shih is on the second semiconductor chip 50.
Yu and Shih do not teach “a third semiconductor chip horizontally spaced apart from the second semiconductor chip, the second molding layer surrounds the first semiconductor chip and the third semiconductor chip, and the first redistribution layer is on the second semiconductor chip, the third semiconductor chip, and the second molding layer.
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In the same field of endeavor, refer to Fig. 14 provided above, Zhai teaches a semiconductor package (para [0025-0051]) comprising: a third semiconductor chip 150-R (para [0042]) horizontally spaced apart from a second semiconductor chip 150-L (para [0042]), a second molding layer 170 (para [0045]) surrounds a first semiconductor chip and the third semiconductor chip, and a first redistribution layer 130 (para [0038]) is on the second semiconductor chip, the third semiconductor chip, and the second molding layer (see Fig. 14).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first chip structure further include a third semiconductor chip horizontally spaced apart from the second semiconductor chip, as taught by Zhai, to create a more robust package.
Note: by placing a third semiconductor die adjacent to the second semiconductor die within the first chip structure the claimed limitations of "the second molding layer surrounds the first semiconductor chip and the third semiconductor chip, and the first redistribution layer is on the second semiconductor chip, the third semiconductor chip, and the second molding layer" would be taught.
Regarding claim 7, refer to the figures cited above, the combination of Yu, Shih and Zhai teach a fourth semiconductor chip 110-R (Zhai) on the first chip structure ("chip struct-1” of Yu) and horizontally spaced apart from the first semiconductor chip 110-L (Zhai), the fourth semiconductor chip being mounted on a first redistribution layer (RDL-1 of Yu = 130-Zhai) of the first chip structure (struct-1 of Yu), wherein the first semiconductor chip 100-Yu is on the second semiconductor chip 50-Yu, and wherein the fourth semiconductor chip is on a third semiconductor chip (150-R of Zhai).
Regarding claim 8, refer to the figures cited above, in the combination of Yu, Shih and Zhai, Zhai teaches a two semiconductor chips (e.g. a first and a fourth) mounted on a first redistribution layer of the first chip structure on the second molding layer., he does not explicitly teach the inclusion of additional chips (e.g. fifth, sixth, etc...).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the number of semiconductor chips to be between the first semiconductor chip and the fourth semiconductor chip on the first chip structure, those semiconductor chips being mounted on the first redistribution layer of the first chip structure and on the second molding layer, since it has been held that the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). It is the Examiner's position that no new and unexpected result is produced, therefore the modification of duplicating parts is not a patentable feature for the invention as claimed. As a result, requiring a rationale for modifying a reference is moot because the modification is, under Harza, not a patentable feature.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Shih, as applied to claim 1 above, and further in view of Chen et al. (PG Pub 20180122764; hereinafter Chen).
Regarding claim 9, refer to the figures cited above, in the combination of Yu and Shih, Yu teaches a first chip structure (“chip struct-1”), he does not teach "a second chip structure spaced apart from the first chip structure on the package substrate, the second chip structure being mounted on the package substrate; and a third semiconductor chip mounted on the second chip structure, wherein the first molding layer surrounds the first chip structure, the first semiconductor chip, the second chip structure, and the third semiconductor chip, wherein the second chip structure comprises: a fourth semiconductor chip; a third molding layer on a lateral surface of the fourth semiconductor chip; a second redistribution layer on the fourth semiconductor chip and the third molding layer; and a second through electrode that vertically penetrates the third molding layer and is connected to the second redistribution layer."
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In the same field of endeavor. refer to Fig. 1I, Chen teaches a chip package structure (para [0015- 0079]) comprising: a second chip structure 200-right (para [0041]) spaced apart from a first chip structure 200-left (para [0041]) on a package substrate 230 (para [0044]), the second chip structure being mounted on the package substrate (see Fig. 1I); and a third semiconductor chip 130 (chip-3) mounted on the second chip structure (see Fig. 1I), wherein a first molding layer 240 surrounds the first chip structure, a first semiconductor chip 130 ("chip-1"), the second chip structure, and the third semiconductor chip (see Fig. 1I), wherein the second chip structure comprises: a fourth semiconductor chip 170 (chip-4); a third molding layer 180 ("mold-3") on a lateral surface of the fourth semiconductor chip (see Fig. 1I); a second redistribution layer ("RDL-2") on the fourth semiconductor chip and the third molding layer (see Fig. 1I); and a second through electrode 160 (elec-2) that vertically penetrates the third molding layer and is connected to the second redistribution layer (see Fig. 1I).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second chip structure, as taught by Chen, into the package of Yu, to create a more robust package.
Claim(s) 15-16, 21-22, 25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub 2021/0134730; hereinafter Yu) and Shih et al (PG Pub 2018/0102311; hereinafter Shih) and Kim et al. (PG Pub 2020/0043853; hereinafter Kim).
Regarding claim 15, refer to the Examiner’s mark-up of Fig. 16, Yu teaches a semiconductor package, comprising:
a package substrate 148;
a first semiconductor chip flip-chip 50 mounted on the package substrate and having an inactive top surface (para [0060]; “communication between the top dies 50 and the bottom dies 100 goes through the redistribution structure 148”; see Fig. 16);
a first molding layer 133 that surrounds a lateral surface of the first semiconductor chip (see Fig. 16);
a first through electrode 131 that vertically penetrates the first molding layer and is mounted on the package substrate;
a second molding layer 143 disposed on the package substrate, the second molding layer covering the first molding layer, the first redistribution layer (bonding layer), and the second semiconductor chip (see Fig. 160.
Yu does not teach the first through electrode is mounted on the package substrate through a first connection terminal on the bottom surface of the first molding layer.
In the same field of endeavor, refer to Fig. 2-provided above, Kim teaches a semiconductor device comprising: a first through electrode 220 is mounted on a package substrate 100 through a first connection terminal 270 on the bottom surface of the first molding layer (see Fig. 2).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mount the first through electrode to the package substrate through a second connection terminal, as taught by Kim, to provide a way to communicate with external devices.
Although, Yu teaches the first and second die are connected to one another through a bonding layer, he does not explicitly teach the details of this bonding layer; such that this bonding layer is “a first redistribution layer disposed on the first semiconductor chip and the first molding layer, the first redistribution layer being electrically coupled to the first through electrode; a second semiconductor chip flip-chip mounted on the first redistribution layer in a stacking direction; and wherein the second molding layer overlaps the second semiconductor chip in the stacking direction.
In the same field of endeavor, refer to Fig.14-provided above, Shih teaches a semiconductor package comprising: a first redistribution layer 900 disposed on a first semiconductor chip 101 and a first molding layer 550, the first redistribution layer being electrically coupled to a first through electrode 510; a second semiconductor chip 11 flip-chip mounted (para [0051]) on the first redistribution layer in a stacking direction (see Fig. 13); and wherein a second molding layer overlaps the second semiconductor chip in the stacking direction.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the bonding layer of Yu with the redistribution layer of Shih, to provide electrical communication to the second semiconductor chip and potentially additional chips.
Note: by exchanging the bonding layer of Yu, with the redistribution layer of Shih, between the first and second semiconductor chip a portion of the second molding layer would overlap the second semiconductor chip in the stacking direction.
Regarding claim 16, refer to the figures cited above, the combination of Yu, Kim and Shih teach
at least a portion of the second semiconductor chip 100 vertically overlaps the first molding layer 133 (see Fig. 16).
Regarding claim 21, refer to the Examiner’s mark-up of Fig. 16, Yu teaches a semiconductor package, comprising:
a package substrate 148;
a first chip structure (“chip struct-1”) on the package substrate (see Fig. 16); and
a first semiconductor chip 100 on the first chip structure (see Fig. 16); wherein the first chip structure comprises:
a second semiconductor chip 50 having an inactive top surface (para [0060]; “communication between the top dies 50 and the bottom dies 100 goes through the redistribution structure 148”);
a vertical connection terminal 131 on a side (left/right) of the second semiconductor chip (see Fig. 16);
wherein the second semiconductor chip is mounted on the package substrate through a first connection terminal 55 between the package substrate and the second semiconductor chip (see Fig. 16).
Yu does not teach the vertical connection terminal is mounted on the package substrate through a second connection terminal between the package substrate and the vertical connection terminal.
In the same field of endeavor, refer to Fig. 2-provided above, Kim teaches a semiconductor device comprising: vertical connection terminal 220 is mounted on a package substrate 100 through a second connection terminal 270 between the package substrate and the vertical connection terminal (see Fig. 2).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mount the first through electrode to the package substrate through a second connection terminal, as taught by Kim, to provide a way to communicate with external devices.
Although, Yu teaches the first and second die are connected to one another through a layer, he does not explicitly teach the details of this layer; such that this layer is “a first redistribution layer on the second semiconductor chip and the vertical connection terminal, the first redistribution layer being electrically connected to the vertical connection terminal, and on which is mounted the first semiconductor chip, and wherein the first redistribution layer is wider than the first semiconductor chip and comprises a substrate wiring layer which includes a substrate dielectric pattern and a substrate wiring pattern in the substrate dielectric pattern.”
In the same field of endeavor, refer to Fig.14-provided above, Shih teaches a semiconductor package comprising: a first redistribution layer 900 on the second semiconductor chip and the vertical connection terminal, the first redistribution layer being electrically connected to the vertical connection terminal, and on which is mounted the first semiconductor chip, and wherein the first redistribution layer is wider than the first semiconductor chip and comprises a substrate wiring layer which includes a substrate dielectric pattern and a substrate wiring pattern in the substrate dielectric pattern.”
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the bonding layer of Yu with the redistribution layer of Shih, to provide electrical communication to the second semiconductor chip and potentially additional chips.
Note: by exchanging the bonding layer of Yu, with the redistribution layer of Shih, between the first and second semiconductor chip a portion of the first molding layer of Yu would be disposed directly on an uppermost surface of the first redistribution layer (see cited figures above).
Regarding claim 22, refer to the cited figures above, Yu, Kim and Shih teach the first chip structure (“chip struct-1”) further includes a first molding layer (133-Yu = 500-Shih) that surrounds the second semiconductor chip 50, the first redistribution layer 900-Shih covers the first molding layer and the second semiconductor chip (see figures above), and the vertical connection terminal 131 includes a through electrode that vertically penetrates the first molding layer, the through electrode being coupled to the first redistribution layer (see figures above).
Regarding claim 25, refer to the cited figures above, Yu, Kim and Shih the second semiconductor chip 50 is in a face-down state on the package substrate 148 (see Fig. 16), and the first redistribution layer 900-Shih is on the inactive top surface of the second semiconductor chip (900 of Shih replaces the bonding layer).
Regarding claim 27, refer to the cited figures above, Yu, Kim and Shih at least a portion of the first semiconductor chip 100 vertically overlaps the first molding layer 131 (see Fig. 16).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Kim and Shih, as applied to claim 15 above, and further in view of Chen et al. (PG Pub 20180122764; hereinafter Chen).
Regarding claim 17, refer to the figures cited above, the combination of Yu, Kim and Shih, Yu teaches the first semiconductor chip 50 and flip-chip mounted on the package substrate 148 (see Fig. 16), Yu does not teach "a third semiconductor chip horizontally spaced apart from the first semiconductor chip and flip-chip mounted on the package substrate, wherein the first molding layer surrounds the first semiconductor chip and the third semiconductor chip, and wherein the first redistribution layer is on the first semiconductor chip, the third semiconductor chip, and the first molding layer."
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In the same field of endeavor. refer to Fig. 1I, Chen teaches a chip package structure (para [0015- 0079]) comprising: a third semiconductor chip 170 horizontally spaced apart from a first semiconductor chip 170 and flip-chip mounted on a package substrate 230 (see Fig. 1I), wherein a first molding layer 180 surrounds the first semiconductor chip and the third semiconductor chip (see Fig. 1I),
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second chip structure, as taught by Chen, into the package of Yu, to create a more robust package.
Note: by adding a third chip adjacent to the first chip of Yu, the first redistribution layer of Shih would be on the first semiconductor chip, the third semiconductor chip, and the first molding layer.
Allowable Subject Matter
6. Claims 10, 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 10, a fifth semiconductor chip between the first semiconductor chip and the third semiconductor chip, wherein the fifth semiconductor chip overlaps a portion of the first chip structure and a portion of the second chip structure.
Claim 12 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 12, a second chip structure mounted on the first chip structure, wherein the second chip structure comprises: a third semiconductor chip; a third molding layer on a lateral surface of the ninth semiconductor chip; a second redistribution layer on the third semiconductor chip and the third molding layer; and a second through electrode that vertically penetrates the third molding layer and is connected to the second redistribution layer, wherein the first semiconductor chip is mounted on the second chip structure and is connected to the first redistribution layer of the first chip structure through the second through electrode and the second redistribution layer of the second chip structure.
Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, a connection substrate below the first redistribution layer and coupled to the first redistribution layer, the connection substrate having an opening that penetrates the connection substrate, wherein the second semiconductor chip is in the opening of the connection substrate, wherein, in the opening, the second molding layer fills a space between the connection substrate and the second semiconductor chip, and wherein the first through electrode corresponds to a wiring pattern in the connection substrate.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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