Prosecution Insights
Last updated: August 17, 2026
Application No. 18/320,456

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Final Rejection §102
Filed
May 19, 2023
Priority
Oct 17, 2022 — RE 10-2022-0133272 +1 more
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
568 granted / 667 resolved
+17.2% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
702
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
42.3%
+2.3% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
27.3%
-12.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 667 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 6/5/2026. Claims 1-22 are pending. Claims 11-20 are withdrawn. Claims 21-22 are new. Claims 1 and 10 are currently amended. Claims 1 and 10 are independent. Response to Arguments Applicants’ arguments and amendments, filed 6/5/2026, with respect to Prior Art Rejections of independent claim 1, as indicated in line numbers 2-4 of the office action mailed 3/17/2026, have been fully considered and are persuasive. The rejections have been withdrawn, and independent claim 1 is allowed as noted below in the section “Allowable Subject Matter”. Applicants' arguments and amendments, filed 6/5/2026, with respect to independent claim 10, although substantive and pertinent to expediting the prosecution of the current application, are considered moot and not persuasive, respectfully, in light of new grounds of rejections made using the prior art of Tsai, specifically the interpretation of the claimed “first connection element” as element 130 and the claimed “first molding layer” as element 156 in Tsai, as noted below in the rejection of independent claim 10. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2021/0305226 A1, hereinafter “Tsai”). Regarding independent claim 10, Figure 4 of Tsai discloses a semiconductor package comprising: a first package substrate 300 (“interposer”- ¶0115); a first semiconductor chip 200 (“die”- ¶0096) on the first package substrate 300; a first connection element 130 (“redistribution layer”- ¶0036; see Fig. 1F for notation) horizontally spaced apart from the first semiconductor chip 200 and on the first package substrate 300; a second connection element 155 (“connectors”- ¶0049; see Fig. 3E for notation) on the first connection element 130 and electrically connected to the first connection element 130 (¶0049); a second package 150 (“die stack structure”- ¶0039) on the second connection element 155, the second package 150 including a second package substrate 150d (“dies”- ¶0039) and a second semiconductor chip 150a (“dies”- ¶0039); and a mold layer 156 (“underfill layer”- ¶0050; see Fig. 3E for notation) on the first package substrate 300 and exposing an upper surface of the first semiconductor chip 200 and an upper surface of the first connection element 130, since layer 156 does not cover the upper surfaces of element 130 and chip 200, wherein the mold layer 156 directly contacts the first connection element 130; wherein the second semiconductor chip 150a does not vertically overlap the first semiconductor chip 200. Allowable Subject Matter Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 22, the prior art of record including Jang, Tsai and/or Lin, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the upper surface of the first semiconductor chip and the upper surface of the second connection element are coplanar”. Claims 1-9 and 21 are allowed. Regarding independent claim 1, the claim is allowed, because the prior art of record including Jang, Tsai and/or Lin, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the first semiconductor chip is fully contained within the first region and the second semiconductor chip is fully contained within the second region”. Claims 2-9 and 21 are allowed as being dependent on allowed claim 1. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 19, 2023
Application Filed
Mar 17, 2026
Non-Final Rejection mailed — §102
Apr 27, 2026
Applicant Interview (Telephonic)
Apr 27, 2026
Examiner Interview Summary
Jun 05, 2026
Response Filed
Jul 15, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707977
INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
3y 7m to grant Granted Aug 11, 2026
Patent 12690486
Subtractive Metal Structuring on Surface of Semiconductor Package
3y 4m to grant Granted Jul 21, 2026
Patent 12685099
Method of Multi-layer Die Stacking with Die-to-Wafer Bonding
3y 5m to grant Granted Jul 14, 2026
Patent 12685069
MANUFACTURING METHOD OF THE SEMICONDUCTOR PACKAGE, PICK AND PLACE DEVICE, AND WORKPIECE HANDLING APPARATUS
3y 5m to grant Granted Jul 14, 2026
Patent 12660672
ANTENNA PACKAGE
3y 4m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+14.0%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 667 resolved cases by this examiner. Grant probability derived from career allowance rate.

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