DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/19/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of Group I in the reply filed on 2/17/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/17/2026.
A. Prior-art rejections based at least in part by Jang
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang (US 2016/0118366 A1).
Regarding independent claim 1, Figure 3B of Jang discloses a semiconductor package comprising:
a first package substrate 110 (“substrate”- ¶0050) having a first region (i.e., the region of 110 vertically overlapped by 120) and a second region (i.e., the region of 110 vertically overlapped by 150), which do not overlap each other;
a first connection element 115 (“connection terminals”- ¶0051) having a first height on the first region;
a first semiconductor chip 120 (“semiconductor chip”- ¶0051) having a second height connected to the first connection element 115;
a second connection element 150 (“connecting portions”- ¶0056) having a third height on the second region;
a third connection element 201 (“interposers”- ¶0073) having a fourth height on the second connection element 150 and electrically connected to the second connection element 150 (¶0073);
a second package 200 (“package”- ¶0050) on the third connection element 201, the second package 200 including a second package substrate 210 (“substrate”- ¶0055) and a second semiconductor chip 220 (“semiconductor chip”- ¶0055); and
a first mold layer 130 (“mold layer”- ¶0050) covering at least a portion of the first semiconductor chip 120, covering at least a portion of the second connection element 150, covering at least a portion of the first package substrate 110, exposing an upper surface of the first semiconductor chip 120 and an upper surface of the second connection element 150, and having a fifth height.
Regarding claim 2, Figure 3B of Jang discloses the semiconductor package further comprising a heat slug 320 (“heat slug”- ¶0058) on the upper surface of the first semiconductor chip 120.
Regarding claim 3, Figure 3B of Jang discloses the semiconductor package further comprising a thermal interface material (TIM) 310 (“thermal interface material”- ¶0058) between the first semiconductor chip 120 and the heat slug 320.
Regarding claim 4, Figure 3B of Jang discloses the semiconductor package further comprising a second mold layer 230 (“mold layer”- ¶0055) covering at least a portion of the second semiconductor chip 220 and at least a portion of the second package substrate 210.
Regarding claim 5, Figure 3B of Jang discloses the wherein an upper surface of the second mold layer 230 and an upper surface of the heat slug 320 are coplanar with each other.
Regarding claim 7, Figure 3B of Jang discloses wherein the upper surface of the first semiconductor chip 120 and an upper surface of the first mold layer 130 are coplanar with each other.
B. Prior-art rejections based at least in part by Jang
Claim Rejections - 35 USC § 102
Claims 1, 6 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2021/0305226 A1, hereinafter “Tsai”).
Regarding independent claim 1, Figure 4 of Tsai discloses a semiconductor package comprising:
a first package substrate 300 (“interposer”- ¶0115) having a first region (i.e., the region of 300 overlapped by 200) and a second region (i.e., the region of 300 overlapped by S1), which do not overlap each other;
a first connection element 307 (“connectors”- ¶0117) having a first height on the first region;
a first semiconductor chip 200 (“die”- ¶0096) having a second height connected to the first connection element 307;
a second connection element 109 (“conductive vias”- ¶0020; see Fig. 1A for notation) having a third height on the second region;
a third connection element 155 (“connectors”- ¶0049; see Fig. 3E for notation) having a fourth height on the second connection element 109 and electrically connected to the second connection element 109 (¶¶0035, 0049);
a second package 150 (“die stack structure”- ¶0039) on the third connection element 155, the second package 150 including a second package substrate 150d (“dies”- ¶0039) and a second semiconductor chip 150a (“dies”- ¶¶0041-0042); and
a first mold layer 212 (“encapsulant”- ¶0099) covering at least a portion of the first semiconductor chip 200, covering at least a portion of the second connection element 109, covering at least a portion of the first package substrate 300, exposing an upper surface of the first semiconductor chip 200 and an upper surface of the second connection element 109, and having a fifth height.
Regarding claim 6, Figure 4 of Tsai discloses the semiconductor package further comprising an underfill layer 308 (“underfill layer”- ¶0118) between the first package substrate 300 and the first semiconductor chip 200.
Regarding independent claim 10, Figure 4 of Tsai discloses a semiconductor package comprising:
a first package substrate 300 (“interposer”- ¶0115);
a first semiconductor chip 200 (“die”- ¶0096) on the first package substrate 300;
a first connection element 109 (“conductive vias”- ¶0020; see Fig. 1A for notation) horizontally spaced apart from the first semiconductor chip 200 and on the first package substrate 300;
a second connection element 155 (“connectors”- ¶0049; see Fig. 3E for notation) on the first connection element 109 and electrically connected to the first connection element 109 (¶¶0035, 0049);
a second package 150 (“die stack structure”- ¶0039) on the second connection element 155, the second package 150 including a second package substrate 150d (“dies”- ¶0039) and a second semiconductor chip 150a (“dies”- ¶0039); and
a mold layer 212 (“encapsulant”- ¶0099) on the first package substrate 300 and exposing an upper surface of the first semiconductor chip 200 and an upper surface of the first connection element 109,
wherein the second semiconductor chip 150a does not vertically overlap the first semiconductor chip 200.
C. Prior-art rejections based at least in part by Lin
Claim Rejections - 35 USC § 102
Claims 1 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2013/0292831 A1, hereinafter “Lin”).
Regarding independent claim 1, Figure 1(b) of Lin discloses a semiconductor package comprising:
a first package substrate 104 (“substrate”- ¶0013) having a first region (i.e., the region of 104 overlapped by 102) and a second region (i.e., the region of 104 overlapped by 31), which do not overlap each other;
a first connection element 120 (“connectors”- ¶0013) having a first height on the first region;
a first semiconductor chip 102 (“die”- ¶0014) having a second height connected to the first connection element 120;
a second connection element 31 (“connectors”- ¶0015) having a third height on the second region;
a third connection element 221 (“connectors”- ¶0015) having a fourth height on the second connection element 31 and electrically connected to the second connection element 31;
a second package 106/108 (collectively 106 and 108) on the third connection element 221, the second package 106/108 including a second package substrate 108 (“substrate”- ¶0011) and a second semiconductor chip 106 (“die”- ¶0012); and
a first mold layer 230 (“encapsulant”- ¶0015) covering at least a portion of the first semiconductor chip 102, covering at least a portion of the second connection element 31, covering at least a portion of the first package substrate 104, exposing an upper surface of the first semiconductor chip 102 and an upper surface of the second connection element 31, and having a fifth height.
Regarding claim 7, Figure 1(b) of Lin discloses wherein the upper surface of the first semiconductor chip 102 and an upper surface of the first mold layer 230 are coplanar with each other.
Regarding claim 8, Figure 1(b) of Lin discloses wherein the upper surface of the second connection element 31 and the upper surface of the first mold layer 230 are coplanar with each other.
Regarding claim 9, Figure 1(b) of Lin discloses wherein the third height of the second connection element 31 is equal to a sum of the first height of the first connection element 120 and the second height of the first semiconductor chip 102.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen et al. (US 2021/0066263 A1), which discloses a semiconductor package comprising a semiconductor chip and a first connection element on a package substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817