DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 6, Fig. 24, claims 1-7, 13-16 and 18-20 in the reply filed on February 26, 2026 is acknowledged. Claims 8-12 and 17 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 13-16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) (US 2022/0059437 A1) in view of Lee et al. (Lee) (US 2018/0197827 A1).
In regards to claim 1, Kim (Figs. 6, 8 and associated text and items) discloses a semiconductor package (Figs. 6, 8, items 100D plus 200, paragraph 65) comprising: a first redistribution structure (item 140, paragraph 21) including a first redistribution layer (item 142); a first semiconductor chip (item 120) on the first redistribution structure (item 140); an insulating layer (items 111a plus 111b) adjacent a sidewall of the first semiconductor chip (item 120) on the first redistribution structure (item 140), wherein the insulating layer (items 111a plus 111b) is spaced apart from the first semiconductor chip (item 120) in a horizontal direction; a connection structure (items 112a plus 112b plus 112c plus 113a plus 113b) extending through the insulating layer (items 111a plus 111b) in a vertical direction, wherein the connection structure (items 112a plus 112b plus 112c plus 113a plus 113b) is electrically connected to the first redistribution layer (item 140); a first molding layer (item 130) on a sidewall and a top surface of the first semiconductor chip (item 120); and a second molding layer (items 135) indirectly on each of a top surface of the insulating layer (items 111a plus 111b) and directly on a top surface of the first molding layer (item 130, Fig. 6), wherein the second molding layer (item 135, paragraph 59) includes a material different from a material of the first molding layer (item 130, paragraph 29).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate various embodiments of Kim for the purpose of various semiconductor package configurations other than 300A (paragraph 65).
Kim does not specifically disclose a second molding layer directly on each of a top surface of the insulating layer and a top surface of the first molding layer …wherein the top surface of the first semiconductor chip is lower than the top surface of the insulating layer relative to the first redistribution structure.
Lee (Figs 12, 13, and associated text and items) discloses a second molding layer (item 152) directly on each of a top surface of the insulating layer (item 110) and a top surface of the first molding layer (item 151), which are different materials (paragraph 71)…wherein the top surface of the first semiconductor chip (item120) is lower than the top surface of the insulating layer (item 110) relative to the first redistribution structure (item 130).
Therefor it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching so Lee for the purpose of firmly securing the semiconductor chip, reducing warpage (paragraph 71).
In regards to claim 2, Kim as modified by Lee (Figs 12, 13, and associated text and items) discloses wherein a viscosity of the first molding layer (item 151) is lower than a viscosity of the second molding layer (item 152, paragraph 89).
Therefor it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching so Lee for the purpose of firmly of preventing degradation in filling properties which may cause voids (paragraph 89).
In regards to claim 3, Kim as modified by Lee (Figs 12, 13, and associated text and items) discloses wherein the connection structure (item 113) does not contact the first molding layer (item 151).
In regards to claim 4, Kim as modified by Lee (Figs 12, 13, and associated text and items) discloses wherein at least a portion of the connection structure (item 113) directly contacts the second molding layer (item 152).
In regards to claim 5, Kim (Figs. 6, 8 and associated text and items) as modified by Lee discloses further comprising: a second redistribution structure (item 170 plus 180 paragraph 42) on the second molding layer (item 135), the second redistribution structure (item 170 plus 180) includes a second redistribution layer (item 171, 173 or 171 plus 173) therein.
In regards to claim 6, Kim (Figs. 6, 8 and associated text and items) as modified by Lee discloses further comprising: a substrate (item 210) on the second redistribution structure (item 170 plus 180, paragraph 42) and electrically connected to the second redistribution structure (item 170 plus 180); and a second semiconductor chip (item 220) on the substrate (item 210).
In regards to claim 7, Kim (Figs. 6, 8 and associated text and items) as modified by Lee discloses wherein the top surface of the first molding layer (item 130) is (vertically) coplanar with the top surface of the insulating layer (item 111a plus 111b). Examiner notes the Applicant has not established and/or claimed whether these tops surfaces are horizontally or vertically coplanar.
In regards to claim 13, Kim (Figs. 6, 8 and associated text and items) discloses a semiconductor package (Figs. 6, 8, items 100D plus 200, paragraph 65) comprising: a first redistribution structure (item 140, paragraph 21) including a first redistribution layer (item 142); an insulating layer (items 111a plus 111b) on the first redistribution structure (item 140); a recess (item 110H) in the insulating layer (items 111a plus 111b); a first semiconductor chip (item 120) in the recess (item 110H) and spaced apart from the insulating layer (items 111a plus 111b) in a horizontal direction…; a first molding layer (item 130) on a sidewall and the top surface of the first semiconductor chip (item 120) in the recess (item 110H), wherein the first molding layer (item 130) is free of a filling material including silicon (Si) particles; and a second molding layer (item 135) indirectly on the top surface of the insulating layer and directly on a top surface of the first molding layer (item 130).
Kim does not specifically disclose wherein a top surface of the first semiconductor chip is lower than a top surface of the insulating layer relative to the first redistribution structure…and a second molding layer directly on each of the top surface of the insulating layer and a top surface of the first molding layer.
Lee (Figs 12, 13, and associated text and items) discloses wherein the top surface of the first semiconductor chip (item120) is lower than the top surface of the insulating layer (item 110) relative to the first redistribution structure (item 130)… and a second molding layer (item 152) directly on each of a top surface of the insulating layer (item 110) and a top surface of the first molding layer (item 151), which are different materials (paragraph 71)
Therefor it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching so Lee for the purpose of firmly securing the semiconductor chip, reducing warpage (paragraph 71).
Kim as modified by Lee does not specifically disclose wherein the second molding layer comprises the filling material including silicon (Si) particles.
It would have been obvious to modify the invention to include a second molding layer comprises a filling material including silicon (Si) particles, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 14, Kim as modified by Lee (Figs 12, 13, and associated text and items) discloses further comprising: a connection structure (item 113) extending through the insulating layer (item 110) in a vertical direction, wherein the connection structure (item 113) is electrically connected to the first redistribution layer (item 130), and the connection structure does not contact the first molding layer (item 151).
In regards to claim 15, Kim as modified by Lee (Figs 12, 13, and associated text and items) discloses wherein the first molding layer (item 151) does not contact the top surface of the insulating layer (item 110).
In regards to claim 16, Kim (Figs. 6, 8 and associated text and items) as modified by Lee discloses further comprising: a second redistribution structure (item 170 plus 180 paragraph 42) on the second molding layer (item 135), the second redistribution structure (item 170 plus 180) includes a second redistribution layer (item 171, 173 or 171 plus 173) therein.
In regards to claim 18, Kim (Figs. 6, 8 and associated text and items) as modified by Lee discloses further comprising: a connection structure (items 112a plus 112b plus 112c plus 113a plus 113b) extending through the insulating layer (items 111a plus 111b) in a vertical direction, wherein the connection structure (items 112a plus 112b plus 112c plus 113a plus 113b) is electrically connected to the first redistribution layer (item 142); a connection pad (item 173) on a top surface of the second molding layer (item 135); and a via (item 171) extending through the second molding layer (item 135) in the vertical direction, wherein the via (item 171) electrically connects the connection structure (items 112a plus 112b plus 112c plus 113a plus 113b) to the connection pad (item 173).
In regards to claim 19, Kim (Figs. 6, 8 and associated text and items) as modified by Lee discloses further comprising: a substrate (item 210) on the second molding layer (item 135) and electrically connected to the connection pad (item 173); and a second semiconductor chip (item 220) on the substrate (item 210).
In regards to claim 20, Kim (Figs. 6, 8 and associated text and items) discloses a semiconductor package (Figs. 6, 8, items 100D plus 200, paragraph 65) comprising: a first redistribution structure (item 140, paragraph 21) including a first redistribution layer (item 142); a first semiconductor chip (item 120) on the first redistribution structure (item 140); an insulating layer (items 111a plus 111b) adjacent a sidewall of the first semiconductor chip (item 120) on the first redistribution structure (item 140), wherein the insulating layer (items 111a plus 111b) is spaced apart from the first semiconductor chip (item 120) in a horizontal direction; a connection structure (items 112a plus 112b plus 112c plus 113a plus 113b) extending through the insulating layer (items 111a plus 111b) in a vertical direction, wherein the connection structure (items 112a plus 112b plus 112c plus 113a plus 113b) is electrically connected to the first redistribution layer (item 140); a first molding layer (item 130) on the sidewall and a top surface of the first semiconductor chip (item 120), wherein the first molding layer (item 130) is free of a filling material including silicon (Si) particles… a second molding layer (item 135) indirectly on a top surface of the insulating layer (items 111a plus 111b) and directly on a top surface of the first molding layer (item 130)… and a second redistribution structure (item 170 plus 180 paragraph 42) on the second molding layer (item 135), the second redistribution structure (item 170 plus 180) includes a second redistribution layer (item 171, 173 or 171 plus 173) therein… wherein the top surface of the first molding layer (item 130) is (vertically) coplanar with the top surface of the insulating layer (items 111a plus 111b). Examiner notes that Applicant has not established and/or claims that these surfaces are horizontally or vertically coplanar.
Kim does not specifically disclose the first molding layer does not contact the connection structure; a second molding layer directly on each of a top surface of the insulating layer and a top surface of the first molding layer, wherein the second molding layer directly contacts at least a portion of the connection structure… wherein the top surface of the first semiconductor chip is lower than the top surface of the insulating layer relative to the first redistribution structure, and wherein the top surface of the first molding layer is coplanar with the top surface of the insulating layer.
Lee (Figs 12, 13, and associated text and items) discloses the first molding layer (item 151) does not contact the connection structure (item 113); a second molding layer (item 152) directly on each of a top surface of the insulating layer (item 110) and a top surface of the first molding layer (item 151), wherein the second molding layer (item 152) directly contacts at least a portion of the connection structure (item 113)… wherein the top surface of the first semiconductor chip (item 120) is lower than the top surface of the insulating layer (item 110) relative to the first redistribution structure (item 130).
Therefor it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching so Lee for the purpose of firmly securing the semiconductor chip, reducing warpage (paragraph 71).
Kim as modified by Lee does not specifically disclose the second molding layer comprises the filling material including silicon (Si) particles.
It would have been obvious to modify the invention to include a second molding layer comprises a filling material including silicon (Si) particles, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 March 27, 2026