DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/19/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: a second semiconductor chip. Applicant claims a relationship between a first and third semiconductor chip without making claim to a second semiconductor chip.
Claims 10-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “dummy pattern” in claim 10 is used by the claim to mean “an electrically connected pattern,” while the accepted meaning is “a pattern which is not electrically connected to anything.” The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-9, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Publication No. 2023/0187307) in view of Tseng et al. (US Publication No. 2021/0305112).
Regarding claim 1, Yu discloses a semiconductor package comprising (Figure 60):
a first redistribution substrate (230)
a first semiconductor chip (210) on the first redistribution substrate (230)
a heat dissipation layer (516) on the first semiconductor chip (210) and in contact with an upper surface of the first semiconductor chip (210)
a second redistribution substrate (248) on the heat dissipation layer (516)
a molding layer (228) surrounding the first semiconductor chip (210) and the heat dissipation layer (516) between the first redistribution substrate (230) and the second redistribution substrate (248)
through electrodes (226) vertically penetrating the molding layer (228) and electrically connecting the first redistribution substrate (230) and the second redistribution substrate (248), the through electrodes being spaced apart from the first semiconductor chip (210) and the heat dissipation layer (516)
dummy patterns (506) vertically penetrating the molding layer (226) and in contact with a side surface of the first semiconductor chip (210) and a side surface of the heat dissipation layer (516) (paragraph 172)
wherein the first redistribution substrate (230) includes a first insulating layer (234), first wiring patterns (below 138) in the first insulating layer (234), and second wiring patterns (232) in the first insulating layer (234), electrically connected to the dummy patterns (506), and electrically insulated from the first wiring patterns (below 138)
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Yu is silent regarding the first wiring patterns in the first insulating layer electrically connecting the first semiconductor chip and the through electrodes. However, Tseng discloses a first wiring pattern (136) which electrically connects the chip (105) to the through electrodes (136). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Yu to include an electrical connection between the chip and through electrodes, as taught by Tseng, to redistribute the connection of the chip to additional packages above the chip, thereby increasing the density of the packages, increasing speed while maintaining heat dissipation and reducing package warping (paragraphs 41-42).
Regarding claim 2, Yu discloses the dummy patterns (506) include a metal (paragraph 179).
Regarding claim 4, Tseng discloses a second semiconductor chip mounted on the second redistribution substrate through a chip connection terminal (Figure 10). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Tseng.
Regarding claim 5, Tseng discloses the second redistribution substrate (130) includes: a second insulating layer (130); third wiring patterns (134) in the second insulating layer and electrically connected to the second semiconductor chip (165); and fourth wiring patterns in the second insulating layer, connected to the dummy patterns (138), and electrically insulated from the third wiring patterns (Figure 10; paragraph 31). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Tseng.
Regarding claim 6, Tseng discloses a third semiconductor chip (165) between the first semiconductor chip (110) and the second redistribution substrate (160), wherein the heat dissipation layer (168) is between the first semiconductor chip (110) and the third semiconductor chip (160) (Figures 10-11). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Tseng.
Regarding claim 7, Tseng discloses the first semiconductor chip (165) includes a chip pad (166) provided on a lower surface of the first semiconductor chip (165), the first wiring patterns (180) include redistribution pads (184) exposed onto the first redistribution substrate (184), and the chip pad (166) and the redistribution pad (184) are in contact with each other and form an integral body (Figure 11). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Tseng.
Regarding claim 8, Yu discloses substrate connection terminals (240) on a lower surface of the first redistribution substrate (230), wherein the substrate connection terminals (240) include first substrate connection terminals connected to the first wiring patterns (below 138) and second substrate connection terminals connected to the second wiring patterns (239) (Figure 60).
Regarding claim 9, Tseng discloses the dummy patterns (168 sidewalls) surround the first semiconductor chip (165) and the heat dissipation layer (168 top). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Tseng.
Regarding claim 17, Yu discloses a semiconductor package comprising:
a first redistribution substrate (230)
a chip structure (304) on the first redistribution substrate (230), the chip structure including a first semiconductor chip (210) and a heat dissipation layer (516) in contact with an upper surface of the first semiconductor chip
through electrodes (226) spaced apart from the chip structure (304) on the first redistribution substrate (230)
dummy patterns (506) between the chip structure (304) and the through electrodes (226) on the first redistribution substrate (230) and in contact with a side surface of the chip structure (304)
a molding layer (228) surrounding the chip structure (304), the dummy patterns (506), and the through electrodes (226)
a second redistribution substrate (248) covering the molding layer (228)
wherein the heat dissipation layer (516) includes a metal (paragraph 168)
Yu does not disclose a second semiconductor chip mounted on the second redistribution substrate through a chip connection terminal. However, Tseng discloses a second semiconductor chip (105) mounted on the second substrate (130) through a chip connection terminal (138). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Yu to include as second semiconductor substrate, as taught by Tseng, to redistribute the connection of the chip to additional packages above the chip, thereby increasing the density of the packages, increasing speed while maintaining heat dissipation and reducing package warping (paragraphs 41-42).
Regarding claim 18, Yu discloses wherein the first redistribution substrate (230) includes a first insulating layer (234), first wiring patterns (below 138) in the first insulating layer (234), and second wiring patterns (232) in the first insulating layer (234), electrically connected to the dummy patterns (506), and electrically insulated from the first wiring patterns (below 138) and Tseng discloses a first wiring pattern (136) which electrically connects the chip (105) to the through electrodes (136), and the second redistribution substrate (130) includes: a second insulating layer (130); third wiring patterns (134) in the second insulating layer and electrically connected to the second semiconductor chip (165); and fourth wiring patterns in the second insulating layer, connected to the dummy patterns (138), and electrically insulated from the third wiring patterns (Figure 10; paragraph 31). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Tseng.
Regarding claim 20, Tseng discloses the first semiconductor chip (165) includes a chip pad (166) on a lower surface of the first semiconductor chip (165), the first wiring patterns (180) include redistribution pads (184) exposed onto the first redistribution substrate (184), and the chip pad (166) and the redistribution pad (184) are in contact with each other and form an integral body (Figure 11).
Claim 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Publication No. 2023/0187307) in view of Park et al. (US Publication No. 2009/0184414).
Regarding claim 10, Yu discloses a semiconductor package comprising:
a first substrate (230)
a chip structure (304) on the first substrate (230), the chip structure including a first semiconductor chip (210) and a heat dissipation layer (516) covering an upper surface of the first semiconductor chip (210)
a second substrate (248) on the chip structure (200)
dummy patterns (506) electrically connecting the first substrate (230) and the second substrate (248) and in contact with a side surface of the chip structure (304)
a connection structure (226) electrically connecting the first substrate (230) and the second substrate (248) and spaced apart from the chip structure (304)
Yu does not disclose the side surface of the first semiconductor chip and the side surface of the heat dissipation layer have a concave portion toward an inside of the first semiconductor chip and an inside of the heat dissipation layer, and at least a portion of a side surface of each of the dummy patterns is in contact with the concave portion. However, Park discloses a concave portion (H) toward an inside of a chip (110) and heat dissipation layer (116/120), with a portion of the dummy pattern (120) in contact with the concave portion (H) (Figures 2E and 3B). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Yu to include a concave portion toward the chip and heat dissipation layer, as taught by Park, since it can enhance heat radiation efficiency while shielding electromagnetic radiation (paragraph 3).
Regarding claim 12, Yu discloses the heat dissipation layer (516) is in contact with an upper surface of the first semiconductor chip (210) (Figure 60).
Claims 11 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Publication No. 2023/0187307) in view of Park et al. (US Publication No. 2009/0184414), and further in view of Tseng et al. (US Publication No. 2021/0305112).
Regarding claim 11, Yu/Park discloses the limitations as discussed in the rejection of claim 10 above. Yu/Park is silent regarding the first wiring patterns in the first insulating layer electrically connecting the first semiconductor chip and the through electrodes. However, Tseng discloses a first wiring pattern (136) which electrically connects the chip (105) to the through electrodes (136). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Yu/Park to include an electrical connection between the chip and through electrodes, as taught by Tseng, to redistribute the connection of the chip to additional packages above the chip, thereby increasing the density of the packages, increasing speed while maintaining heat dissipation and reducing package warping (paragraphs 41-42).
Regarding claim 13, Tseng discloses a second semiconductor chip (105) mounted on the second substrate (130) through a chip connection terminal (138). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Park, and further in view of Tseng.
Regarding claim 14, Tseng discloses the second redistribution substrate (130) includes: a second insulating layer (130); third wiring patterns (134) in the second insulating layer and electrically connected to the second semiconductor chip (165); and fourth wiring patterns (above 150) in the second insulating layer, connected to the dummy patterns (138), and electrically insulated from the third wiring patterns (Figure 10; paragraph 31). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Park, and further in view of Tseng.
Regarding claim 15, Tseng discloses a portion of the fourth wiring patterns (above 150) is exposed onto an upper surface of the second substrate (130). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Park, and further in view of Tseng.
Regarding claim 16, Tseng discloses a third semiconductor chip (110/165) on the second substrate and between the first semiconductor chip and the second substrate, wherein the heat dissipation layer (168) is between the first semiconductor chip and the third semiconductor chip (Figure 11). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Yu in view of Park, and further in view of Tseng.
Claim 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Publication No. 2023/0187307) in view of Tseng et al. (US Publication No. 2021/0305112), and further in view of Park et al. (US Publication No. 2009/0184414).
Regarding claim 3, Yu/Tseng discloses the limitations as discussed in the rejection of claim 1 above. Yu/Tseng does not disclose the side surface of the first semiconductor chip and the side surface of the heat dissipation layer have a concave portion toward an inside of the first semiconductor chip and an inside of the heat dissipation layer, and at least a portion of a side surface of each of the dummy patterns is in contact with the concave portion. However, Park discloses a concave portion (H) toward an inside of a chip (110) and heat dissipation layer (116/120), with a portion of the dummy pattern (120) in contact with the concave portion (H) (Figures 2E and 3B). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Yu/Tseng to include a concave portion toward the chip and heat dissipation layer, as taught by Park, since it can enhance heat radiation efficiency while shielding electromagnetic radiation (paragraph 3).
Regarding claim 19, Yu/Tseng discloses the limitations as discussed in the rejection of claim 17 above. Yu/Tseng does not disclose the side surface of the first semiconductor chip and the side surface of the heat dissipation layer have a concave portion toward an inside of the first semiconductor chip and an inside of the heat dissipation layer, and at least a portion of a side surface of each of the dummy patterns is in contact with the concave portion. However, Park discloses a concave portion (H) toward an inside of a chip (110) and heat dissipation layer (116/120), with a portion of the dummy pattern (120) in contact with the concave portion (H) (Figures 2E and 3B). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Yu/Tseng to include a concave portion toward the chip and heat dissipation layer, as taught by Park, since it can enhance heat radiation efficiency while shielding electromagnetic radiation (paragraph 3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Balakrishnan et al. (US Publication No. 2019/0206839) discloses a thermal conduit on top and side of a chip (106) connected to dummy electrodes (140) (Figure 1A). Sun et al. (US Publication No. 2023/0420330) discloses a metal heat dissipation layer (122) on the top and sidewall of a chip (150).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 2/13/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897