DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 10-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Boo et al. (US Pat 12,148,736, hereinafter Boo).
Regarding claim 1, figure 1A of Boo discloses a semiconductor package, comprising:
a package substrate (102/120) having an upper surface and a lower surface opposite to the upper surface, the package substrate having first substrate pads (132) and second substrate pads (125), the first substrate pads arranged along a side portion thereof, the second substrate pads arranged outside the first substrate pads, being along the side portion, and arranged at positions higher than the first substrate pads;
a first group of semiconductor chips (110b) sequentially stacked on the upper surface of the package substrate, the first group of semiconductor chips including at least one semiconductor chip;
a second group of semiconductor chips (110d) sequentially stacked on the first group of semiconductor chips, the second group of semiconductor chips including at least one semiconductor chip;
first bonding wires (142) electrically connecting first chip pads of the first group of semiconductor chips to the first substrate pads of the package substrate, respectively; and
second bonding wires (144) electrically connecting second chip pads of the second group of semiconductor chips to the second substrate pads of the package substrate, respectively.
Regarding claim 2, figure 1A of Boo discloses the package substrate (102/120) has a stepped portion that extends along the side portion and protrudes from the upper surface of the package substrate to have a thickness, and the second substrate pads (125) are disposed on the stepped portion.
Regarding claim 10, figure 6 of Boo discloses a molding member (650) on the upper surface of the package substrate to cover the first group of semiconductor chip and the second group of semiconductor chips.
Regarding claim 11, figures 1A and 6 of Boo disclose the entire claimed invention as noted in the above rejections.
Regarding claim 12, figure 1A of Boo discloses the package substrate (102/120) has a stepped portion that extends along the side portion and protrudes from the upper surface thereof to have a thickness, and the second substrate pads (125) are on the stepped portion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Boo.
Regarding claims 3 and 13, Boo does not explicitly disclose a height difference between the second substrate pads (125) and the first substrate pads (132) is within a range of 20 µm to 60 µm.
However, it would have been obvious to form the pads to have a height difference within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claims 4-5 and 14-15, Boo does not explicitly disclose when viewed from plan view, a minimum distance between the first (second) substrate pads and the first group of semiconductor chips is at least 400 (550) µm.
However, it would have been obvious to form the pads to have distances from the first group of semiconductor chips within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Boo in view of Park et al. (US Pat 10,319,702, hereinafter Park).
Regarding claims 6 and 16, figure 1A of Boo discloses when viewed from a cross-sectional view, at least one of the first bonding wires (142) connects a first subset of the first chip pads to a corresponding one of the first substrate pads, and
at least one of the second bonding wires (144) connects a second subset of the second chip pads to a corresponding one of the second substrate pads.
Boo does not explicitly disclose when viewed in a plan view, the first subset of the first chip pads and the second subset of the second chip pads are arranged on a same line along one direction, and the at least one of the first bonding wires and the at least one of the second bonding wires partially overlap each other.
In the same field of endeavor, figure 1 of Park discloses when viewed in a plan view, a first subset of first chip pads (110) and a second subset of second chip pads (120) are arranged on a same line along one direction, and at least one of first bonding wires (215) and at least one of second bonding wires (415) partially overlap each other (col. 4, lines 1-3).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to arrange the chip pads and bonding wires in the claimed manner as taught by Park for the purpose of forming a high-density device.
Claims 7-9 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Boo in view of ONO et al. (US PG Pub 2022/0059407, hereinafter Ono).
Regarding claims 7-9 and 17-19, Boo does not explicitly disclose a second semiconductor chip arranged on the package substrate (102/120),
a spacer chip on the package substrate to be spaced apart from the second semiconductor chip,
wherein the first group of semiconductor chips (110b) and the second group of semiconductor chips (110d) are stacked on the second semiconductor chip and the spacer chip, and
wherein the first group of semiconductor chips are electrically connected to the second semiconductor chip by a first channel through the first substrate pads, and the second group of semiconductor chips are electrically connected to the second semiconductor chip by a second channel through the second substrate pads.
In the same field of endeavor, figure 1 of Ono discloses a second semiconductor (controller) chip (20) arranged on a package substrate (10),
a spacer chip (50) on the package substrate to be spaced apart from the second semiconductor chip,
wherein semiconductor chips (30, 31) are stacked on the second semiconductor chip and the spacer chip.
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to stack the first and second groups of semiconductor chips on a controller and spacer chip as taught by Ono for the purpose of forming a high-density memory device with compact size.
Furthermore, it would have been obvious that the first group of semiconductor chips are electrically connected to the second semiconductor chip by a first channel through the first substrate pads, and the second group of semiconductor chips are electrically connected to the second semiconductor chip by a second channel through the second substrate pads in order for the second semiconductor chip to act as a memory controller.
Regarding claim 120 figures 1A and 6 of Boo in view of Ono disclose the entire claimed invention as noted in the above rejections.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817