Prosecution Insights
Last updated: April 19, 2026
Application No. 18/320,618

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND LED DISPLAY DEVICE

Non-Final OA §102
Filed
May 19, 2023
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Oki Electric Industry Co. Ltd.
OA Round
1 (Non-Final)
44%
Grant Probability
Moderate
1-2
OA Rounds
3y 9m
To Grant
94%
With Interview

Examiner Intelligence

Grants 44% of resolved cases
44%
Career Allow Rate
299 granted / 675 resolved
-23.7% vs TC avg
Strong +49% interview lift
Without
With
+49.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
63 currently pending
Career history
738
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 675 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment/Restriction Applicant’s election without traverse of Species I, Embodiment 1, FIG. 2, and Claims 1-16 in the reply filed on February 02, 2026 is acknowledged. Thus, Claim 17 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Election was made without traverse in the reply filed on February 02, 2026. Specification The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-9, 11-12, and 15-16 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2010/0051975 A1 to Suzuki et al. (“Suzuki”). As to claim 1, Suzuki discloses a semiconductor device comprising: a first planarized layer (32-1A) having insulating properties, the first planarized layer (32-1A) having a first surface (bottom) and a second surface (top) opposite the first surface (bottom); a plurality of first semiconductor elements (12, 13, 14 of 10-1) formed on the first surface (bottom) of the first planarized layer (32-1A); and a first groove (33-1) provided in the second surface (top) of the first planarized layer (32-1A), wherein the first groove (33-1) is formed in a region outside the plurality of first semiconductor elements (12, 13, 14 of 10-1) as viewed in a first direction perpendicular to the first surface (bottom) (See Fig. 1, Fig. 2, Fig. 4, Fig. 5, Fig. 6, ¶ 0028, ¶ 0034, ¶ 0035, ¶ 0036, ¶ 0040, ¶ 0041, ¶ 0058, ¶ 0069, ¶ 0070, ¶ 0071, ¶ 0072, ¶ 0079). As to claim 2, Suzuki discloses further comprising a plurality of first connections (17, circular, branch) connected to the plurality of first semiconductor elements (12, 13, 14 of 10-1); wherein the first groove (33-1) is formed in a region outside the plurality of first semiconductor elements (12, 13, 14 of 10-1) and the plurality of first connections (17, circular, branch) as viewed in the first direction (See Fig. 4, Fig. 6, ¶ 0040). As to claim 3, Suzuki further discloses wherein the plurality of first connections (17, circular, branch) are exposed in the second surface (top) of the first planarized layer (32-1A), and electrically connect the plurality of first semiconductor elements (12, 13, 14 of 10-1) to a plurality of other connections (23-1) located on a second surface side of the first planarized layer (32-1A) (See Fig. 4, Fig. 6, ¶ 0040, ¶ 0041). As to claim 4, Suzuki further discloses wherein the first groove (33-1) communicates with an outside of the first planarized layer (32-1A) at an end surface of the first planarized layer (32-1A) in a surface direction along the first surface (bottom) (See Fig. 5, ¶ 0070) (Notes: the first groove of different index optically communicates with an outside of the first planarized layer). As to claim 5, Suzuki further discloses wherein the first groove (33-1) is formed outside at least the plurality of first semiconductor elements (12, 13, 14 of 10-1) to surround the plurality of first semiconductor elements (12, 13, 14 of 10-1), as viewed in the first direction (See Fig. 4, Fig. 6). As to claim 6, Suzuki further discloses wherein the first groove (33-1) is formed outside the plurality of first connections (17, circular, branch) to surround the plurality of first semiconductor elements (12, 13, 14 of 10-1) and the plurality of first connections (17, circular, branch), as viewed in the first direction (See Fig. 4, Fig. 6). As to claim 7, Suzuki further discloses wherein the first groove (33-1) has a grid pattern as viewed in the first direction (See Fig. 4, Fig. 6) (Notes: the limitation “grid” is defined as a framework of parallel bars; grating by collinsdictionary.com). As to claim 8, Suzuki further discloses wherein the first groove (33-1) has a grid pattern as viewed in the first direction (See Fig. 4, Fig. 6) (Notes: the limitation “grid” is defined as a framework of parallel bars; grating by collinsdictionary.com). As to claim 9, Suzuki further discloses wherein the first groove (33-1) extends in a direction having a component in a direction in which the plurality of first semiconductor elements (12, 13, 14 of 10-1) are arranged (See Fig. 5). As to claim 11, Suzuki further discloses wherein the first groove (33-1) is recessed from the second surface (top) toward the first surface (bottom) in the second surface (top) of the first planarized layer (32-1A) (See Fig. 5). As to claim 12, Suzuki further discloses comprising: a first layer (30-1A) including the first planarized layer (32-1A), the plurality of first semiconductor elements (12, 13, 14 of 10-1), the plurality of first connections (17, circular, branch), and the first groove (33-1); a substrate (11 in 30-2A) on which the first layer (30-1A) is stacked such that the second surface (top) of the first planarized layer (32-1A) is in contact with the substrate (11 in 30-2A); a second layer (12 of 10-3) stacked on a surface of the first layer (30-1A) opposite the substrate (11 in 30-2A) and including at least one second semiconductor element (12 of 10-3); and a third layer (13 of 10-3) stacked on a surface of the second layer (12 of 10-3) opposite the first layer (30-1A) and including at least one third semiconductor element (13 of 10-3) (See Fig. 5). As to claim 15, Suzuki further discloses wherein the plurality of first semiconductor elements (12, 13, 14 of 10-1) are light emitting elements (See Fig. 6, ¶ 0079). As to claim 16, Suzuki discloses an LED display device comprising the semiconductor device of claim 15 (See Fig. 6, ¶ 0079). Claim(s) 1-2, 4, and 9-12 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2017/0154873 A1 to Kim et al. (“Kim”). As to claim 1, Kim discloses a semiconductor device comprising: a first planarized layer (160, 260, 240, 210) having insulating properties, the first planarized layer (160, 260, 240, 210) having a first surface (top) and a second surface (bottom) opposite the first surface (top); a plurality of first semiconductor elements (TR2) formed on the first surface (top) of the first planarized layer (160, 260, 240, 210); and a first groove (AG) provided in the second surface (bottom) of the first planarized layer (160, 260, 240, 210), wherein the first groove (AG) is formed in a region outside the plurality of first semiconductor elements (TR2) as viewed in a first direction perpendicular to the first surface (top) (See Fig. 2, Fig. 3, ¶ 0044, ¶ 0045, ¶ 0052, ¶ 0055, ¶ 0058, ¶ 0068). As to claim 2, Kim discloses further comprising a plurality of first connections (CT2) connected to the plurality of first semiconductor elements (TR2); wherein the first groove (AG) is formed in a region outside the plurality of first semiconductor elements (TR2) and the plurality of first connections (CT2) as viewed in the first direction (See Fig. 2, Fig. 3, ¶ 0052). Aa to claim 4, Kim further discloses wherein the first groove (AG) communicates with an outside of the first planarized layer (160, 260, 240, 210) at an end surface of the first planarized layer (160, 260, 240, 210) in a surface direction along the first surface (top) (See Fig. 2) (Notes: the thermal communication between the AG and the outside is established by the closeness to the edge). As to claim 9, Kim further discloses wherein the first groove (AG) extends in a direction having a component in a direction in which the plurality of first semiconductor elements (TR2) are arranged (See Fig. 2). Aa to claim 10, Kim further discloses wherein a depth of the first groove (AG) in the first direction is not more than half a thickness of the first planarized layer (160, 260, 240, 210) in the first direction (See Fig. 2, Fig. 3). As to claim 11, Kim further discloses wherein the first groove (AG) is recessed from the second surface (bottom) toward the first surface (top) in the second surface (bottom) of the first planarized layer (160, 260, 240, 210) (See Fig. 3). Aa to claim 12, Kim further discloses comprising: a first layer (CH2) including the first planarized layer (160, 260, 240, 210), the plurality of first semiconductor elements (TR2), the plurality of first connections (CT2), and the first groove (AG); a substrate (140) on which the first layer (CH2) is stacked such that the second surface (bottom) of the first planarized layer (160, 260, 240, 210) is in contact with the substrate (140); a second layer (110) stacked on a surface of the first layer (CH2) opposite the substrate (140) and including at least one second semiconductor element (TR1); and a third layer (100) stacked on a surface of the second layer (110) opposite the first layer (CH2) and including at least one third semiconductor element (source/drain) (See Fig. 2, ¶ 0044, ¶ 0045). Allowable Subject Matter Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
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Prosecution Timeline

May 19, 2023
Application Filed
Mar 19, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
44%
Grant Probability
94%
With Interview (+49.2%)
3y 9m
Median Time to Grant
Low
PTA Risk
Based on 675 resolved cases by this examiner. Grant probability derived from career allow rate.

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