DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 , 2, 4-7, 10 and 11 are rejected under 35 U.S.C. 102 (a ) (1) as being anticipated by ( Kermalli et al; 10,622,736) . Regarding claim 1, Kermalli et al discloses an integrated circuit comprising a first substrate (see line 2 of the paragraph 4) comprising a first substrate material (first substrate material of Kermalli et al) and wherein the first substrate (see line 2 of the paragraph 4) including a first circuit (see lines 5 and 6 of the paragraph 4) , a second substrate (see line 2 of the paragraph 4) comprising a second substrate material (second substrate material of Kermalli et al) which is different than the first substrate material and wherein the second substrate including a second circuit (see line 7 of the paragraph 4), and a conductive ( inter connect circuit; see line 8 of the paragraph 4) interconnects electrically connecting the first circuit and the second circuit (see lines 9 and 10 of the paragraph 4). Regarding claim 2, wherein the first circuit is a RF circuit (see line 11 of paragraph 4), and the first substrate material (first substrate material of Kermalli et al) is a high resistance substrate. Regarding claim 4, the limitation recited in claim 4 is well known in the amplifier art. Regarding claim s 5 and 6 , wherein the first circuit (see lines 5 and 6 of the paragraph 4) has a capability to have passive components and a matching network . Regarding claim 7, wherein the second circuit (see line 7 of the paragraph 4) has a capability to have an amplifier circuit and the remaining claim 7 limitation is well known in the amplifier art. Regarding claim 10, Kermalli et al further comprising a third substrate (third substrate of Kermalli et al; see line 2 of the paragraph 5) comprising a third substrate material (third substrate material of Kermalli et al) and the third substrate (third substrate of Kermalli et al) including a third circuit (interconnect circuit; see line 8 of the paragraph 5 of Kermalli et al), and wherein the conductive interconnect (interconnect circuit) electrically connects the third circuit (interconnect circuit) to at least one (first circuit) of the first circuit or the second circuit (see lines 8-10 of the paragraph 5 of Kermalli et al). Regarding claim 11, wherein the conductive interconnect (interconnect circuit) includes at at least one (via) of a via, a solder bump, and or a bonding pad. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over ( Kermalli et al; 10,622,736) in view of [ Koya et al (Fig. 1); 11,705,875]. Kermalli et al discloses all the limitations in claim 3 except for that the first substrate material includes glass. Koya et al discloses a semiconductor device comprising the first substrate (2) comprising a glass (see paragraph 15). It would have been obvious to substitute K oya et al’s first substrate material in place of Kermalli et al’s first substrate material since Kermalli et al discloses a generic first substrate material thereby suggesting that any equivalent first substrate material including a glass would have been usable in Kermalli et al’s reference. Claim (s) 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over ( Kermalli et al; 10,622,736) in view of [Zhao et al (Fig. 2); 8,847,689]. Regarding claim 8, Kermalli et al discloses all the limitations in claim 8 excerpt for that the amplifier circuit includes a common source amplifier. Zhao et al discloses an amplifier circuit comprising a common source amplifier (212). It would have been obvious to substitute Zhao et al’s common source amplifier in place of Kermalli et al’s amplifier circuit since Kermalli et al discloses a generic amplifier circuit thereby suggesting that any equivalent amplifier circuit would have been usable in Kermalli et al’s reference. Regarding claim 9, Kermalli et al discloses all the limitations in claim 9 excerpt for that the first circuit includes a common gate circuit, and the second circuit includes a common source circuit , and the conductive interconnect electrically connects the common gate circuit to the common source circuit. Zhao et al discloses an amplifier circuit comprising the first circuit includes a common gate circuit (21 4 ) , the second circuit includes a common source circuit (212) , and the conductive (the connection between the transistors 212 and 214) and interconnect electrically connects the common gate circuit (214) to the common source circuit (212) . It would have been obvious to substitute Zhao et al’s common gate circuit and the common source circuit in place of Kermalli et al’s amplifier circuit since Kermalli et al discloses a generic amplifier circuit thereby suggesting that any equivalent amplifier circuit would have been usable in Kermalli et al’s reference. Reasons for Allowance Claims 12-20 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (703)774-4614. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HENRY CHOE/ Primary Examiner, Art Unit 2843 #2930