DETAILED ACTION
This correspondence is in response to the communications received January 28, 2026. Claims 1-5 and 8-22 are pending. Claims 10, 11, 13, 14 and 20-22 have been withdrawn.
Response to Arguments
Applicant's arguments filed January 28, 2026 have been fully considered but they are not persuasive. The prior art of Lisiansky et al. (US 9,741,817) in view of Yang (US 9,876,068) appear to still fully satisfy each of the claim limitations.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant has made no claim to the benefit of an earlier filing date.
Election/Restrictions
Claims 10, 11, 13, 14 and 20-22 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected method claims and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on October 8, 2025. Applicant's election with traverse of the species restriction in the reply filed on October 8, 2025 is acknowledged. The traversal is on the ground(s), “that the identified claims are specific to the separate species identified in the figures. On the contrary, the independent claims are generic to all species identified in the Office action. As such, the election of species provided herein is solely with respect to the different figures identified in the Office action.” This is not found persuasive because in the previous office action, Examiner explicitly identified features which are associated with only one of the three species identified. Applicant has elected Group I structure claims and Species I and III or Species III. Pursuant to examination including the search and consideration of claims against the prior art, a search for the embodiment of Species III (Fig. 10, especially with the vertical extensions from the lower electrode), does not yield prior art relevant to the embodiment of Species I (Fig. 2’s specific vertical sandwich type MIM capacitor). Therefore, in keeping with the single invention examination aim of the restriction process, an election of only Species III at this time appears to be the appropriate election at this time. The requirement is still deemed proper and is therefore made FINAL.
It is noted that claims 10 and 11 have been withdrawn from consideration as not being directed to the embodiment captured in Species III and Figs. 7-10. The “a second layer of the first dielectric material” aspect does not appear to be directed to the elected species embodiment.
“10. (Original) The semiconductor die of claim 1, wherein the capacitor is a first capacitor, the first dielectric material is a first layer of the first dielectric material, and the via is a first via, the semiconductor die further including a second capacitor in a second via in a second layer of the first dielectric material.”
“11. (Original) The semiconductor die of claim 10, wherein the second capacitor is larger than the first capacitor.”
Claim Rejections - 35 USC § 112
Applicant’s amendments to claims 1 and 5 have overcome the previous 112 rejections which are hereby withdrawn.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 10, a semiconductor die comprising:
a first dielectric material (310) the first metal interconnect in a first metal layer of the semiconductor die, the first metal layer including first electrical traces, the second metal interconnect in a second metal layer of the semiconductor die, the second metal layer different from the first metal layer, the second metal layer including second traces; and
a capacitor (322) at least partially within a via (middle most 320A) extending through the first dielectric material between the first and second metal interconnects, the capacitor including (i) a first electrode corresponding to the first metal interconnect, (ii) a second electrode corresponding to a portion of a material of the second metal interconnect that protrudes into the via, and (iii) a second dielectric material (322, ¶ 0080)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 15, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lisiansky et al. (US 9,741,817) in view of Yang (US 9,876,068).
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Regarding claim 1, the prior art of Lisiansky discloses in Figs. 1-7D, a semiconductor die comprising:
a first dielectric material (“top dielectric layer (hereinafter top layer) 70 and etch-stop dielectric layer (hereinafter stop layer) 60 to provide stop layer segments 62, 64 and 66 and top layer segments 72, 74 and 76.”, col. 3, lines 58-61, hereinafter referred to as ‘FDM’) between a first metal interconnect (“Lower metal layer 50”, col. 3, line 62, and “first metal layer 80”, col. 4, line 8, hereinafter referred to as ‘FMI’) and a second metal interconnect (“second metal layer 120”, col. 5, lines 10-15, “conductive elements (metal plugs or vias) 142 and 144”, col. 5, line 53, “metal layer 132”, col. 6, line 2, hereinafter referred to as ‘SMI’),
the first metal interconnect in a first metal layer of the semiconductor die (FMI is the first metal level above the semiconductor die 201, incorrectly labelled 20 in Fig. 1, “FIG. 1 illustrates a cross section of a portion 201 of a semiconductor die”, col. 3, line 52-53),
the first metal layer including first electrical traces (FML includes trace shaped metal layer 50, “Lower metal layer 50”, col. 3, line 62), the second metal interconnect in a second metal layer of the semiconductor die (SML is formed in the second metal level above semiconductor die 20),
the second metal layer (SML) different from the first metal layer (SML is shaped differently than FML), the second metal layer including second traces (SML includes trace shaped metal 132, “metal layer 132”, col. 6, line 2); and
a capacitor (the collection of elements of 80, “insulator layer 110”, col. 5, lines 10-12, 120, 132, 142, 144, hereinafter referred to as ‘CAP’) at least partially within a via (portions of CAP that are within the discontinuities in 60/70) extending through the first dielectric material between the first and second metal interconnects (extending through 60/70 and between 132 and 50),
the capacitor including (i) a first electrode corresponding to the first metal interconnect (80), (ii) a second electrode corresponding to a portion of a material of the second metal interconnect that protrudes into the via (12/142), and (iii) a second dielectric material (110) in the via (discontinuities in 60/70) between the first and second metal interconnects (between FMI and SMI).
Lisiansky labels the discontinuities 12 and 14 in Fig. 1, as “cavities” (col. 3, line 56), and not explicitly “a via extending through the first dielectric material”.
Yang discloses that the cavity which accommodates the capacitor dielectric layer is described as, “the remaining high-k material 230 in the via cavity forms the MIM capacitor's dielectric layer that separates the two opposing-polarity capacitor plate portions.”, col. 7, lines 46-49.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “a via extending through the first dielectric material”, as disclosed by Yang in the system of Lisiansky, for the purpose of providing a direct through hole that allows for electrical connection from below and from above so as to have an electrically accessible capacitor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Lisiansky et al. disclose the semiconductor die of claim 1,
wherein the capacitor includes a conductive wall (vertical portions of 80, “first metal layer 80”, col. 4, lines 5, hereinafter referred to as ‘CW’) protruding from the first metal interconnect (from 50) toward the second metal interconnect (toward 132),
the conductive wall (CW) between the first dielectric material and the second dielectric material (CW formed between 70 and 110).
Regarding claim 3, the prior art of Lisiansky et al. disclose the semiconductor die of claim 2, wherein the conductive wall includes a same material as the first metal interconnect (both CW and 50 are made of metal).
Regarding claim 4, the prior art of Lisiansky et al. disclose the semiconductor die of claim 1,
the first metal layer is directly adjacent to the second metal layer (no intervening metallization level between first and second metal layers).
Regarding claim 5, the prior art of Lisiansky et al. disclose the semiconductor die of claim 4,
wherein the first metal layer or the second metal layer corresponds to a Metal 1 (M1) layer in the semiconductor die (the first metal 50 is in the first metallization level position).
Regarding claim 15, the prior art of Lisiansky discloses in Figs. 1-7D, a semiconductor component (col. 3, lines 52-53, “FIG. 1 illustrates a cross section of a portion 201 of a semiconductor die.”) comprising:
a first layer of metal (50, “Lower metal layer 50 can be made of conductive materials such as but not limited to Titanium/Titanium Nitride and Aluminum.”, col. 3, lines 62-64);
a second layer of metal (132, “metal layer 132”, col. 6, line 2) adjacent the first layer of metal (adjacent vertically to 50);
a dielectric layer (60/70) between the first and second layers of metal (between 50 and 132);
the dielectric layer including a first dielectric material (“top dielectric layer (hereinafter top layer) 70 and etch-stop dielectric layer (hereinafter stop layer) 60 to provide stop layer segments 62, 64 and 66 and top layer segments 72, 74 and 76.”, col. 3, lines 58-61, hereinafter referred to as ‘FDM’);
a metal protrusion (vertical portions of 80, “first metal layer 80”, col. 4, lines 5, hereinafter referred to as ‘MP’) extending from the first layer of metal (emanating from direction of 50) toward the second layer of metal (toward 132) through a via (discontinuity in 70) in the dielectric layer (70); and
a second dielectric material (“insulator layer 110”, col. 5, lines 10-12), in the via (in the discontinuity 70), the second dielectric material separating the metal protrusion (MP) from the second layer of metal (110 separates the MP from 132)
the second dielectric material different from the first dielectric material (60/70 shaped differently than 110),
the first (60/70) and second (110) dielectric materials to interface with the second layer of metal (132) at different points along a common plane (both 60/70 and 110 make contact along lateral direction with 132) defined by a surface of the second layer of metal facing towards the first layer of metal (lower surface of 132).
Lisiansky labels the discontinuities 12 and 14 in Fig. 1, as “cavities” (col. 3, line 56), and not explicitly “a via in the dielectric layer”.
Yang discloses that the cavity which accommodates the capacitor dielectric layer is described as, “the remaining high-k material 230 in the via cavity forms the MIM capacitor's dielectric layer that separates the two opposing-polarity capacitor plate portions.”, col. 7, lines 46-49.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “a via in the dielectric layer”, as disclosed by Yang in the system of Lisiansky, for the purpose of providing a direct through hole that allows for electrical connection from below and from above so as to have an electrically accessible capacitor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 18, the prior art of Lisiansky et al. disclose the semiconductor die of claim 15,
wherein the metal protrusion is a first metal protrusion (MP associated with lower electrode side),
the semiconductor component including a second metal protrusion (142) extending from the second layer of metal (from 132) toward the first layer of metal (towards 50) through the via (through discontinuity in 70),
the second dielectric material between the first metal protrusion and the second metal protrusion (110 between vertical extensions of 80, which are the MP and 142).
Regarding claim 19, the prior art of Lisiansky et al. disclose the semiconductor die of claim 18,
wherein the first metal protrusion (vertical portions of 80) defines a cavity (space between the two vertical extensions of 80), and the second metal protrusion (142) extends into the cavity (142 extends into space between two vertical extensions of 80).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lisiansky et al. (US 9,741,817) in view of Yang (US 9,876,068) in view of Kim et al. (US 2013/0242643).
Regarding claim 8, the prior art of Lisiansky et al. disclose the semiconductor die of claim 4, however Lisiansky does not disclose,
“further including:
transistors; and
multiple additional metal layers closer to the transistors than the first and second metal layers are to the transistors.”
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Kim discloses in Fig. 1,
further including:
transistors (transistor shown with source/drain region 126a, 126b, gate 120a, etc. Hereinafter referred to as ‘TR’); and
multiple additional metal layers (125a, 128) closer to the transistors than the first and second metal layers are to the transistors (125a, 128 closer to TR than to capacitors shown. The capacitors being the stack of layers including the lower electrode 129b, and the rest of the capacitor layers thereon. The capacitor lower electrode in the equivalent first metallization level and the capacitor second electrode in the equivalent second metallization level.).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further including:
transistors; and
multiple additional metal layers closer to the transistors than the first and second metal layers are to the transistors”, as disclosed by Kim in the system of Lisiansky, for the purpose of providing the transistors to control the signals being manipulated by the capacitors and to create the wiring infrastructure to route all the active signals necessary to operate the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 9, the prior art of Lisiansky et al. disclose the semiconductor die of claim 4, however Lisiansky does not disclose,
“further including:
transistors; and
multiple additional metal layers farther away from the transistors than the first and second metal layers are from the transistors.”
Kim discloses in Fig. 1,
further including:
transistors (transistor shown with source/drain region 126a, 126b, gate 120a, etc. Hereinafter referred to as ‘TR’); and
multiple additional metal layers (140a, 139a, 140c) farther away from the transistors (away from TR) than the first and second metal layers are from the transistors (140a, 139a, 140c closer to the capacitors shown. The capacitors being the stack of layers including the lower electrode 129b, and the rest of the capacitor layers thereon. The capacitor lower electrode in the equivalent first metallization level and the capacitor second electrode in the equivalent second metallization level.).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further including:
transistors; and
multiple additional metal layers farther away from the transistors than the first and second metal layers are from the transistors”, as disclosed by Kim in the system of Lisiansky, for the purpose of providing the transistors to control the signals being manipulated by the capacitors and to create the wiring infrastructure to route all the active signals necessary to operate the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lisiansky et al. (US 9,741,817) in view of Yang (US 9,876,068) in view of Liao (US 2024/0162172).
Regarding claim 12, the prior art of Lisiansky et al. disclose the semiconductor die of claim 1, however Lisiansky does not disclose, “wherein the semiconductor die implements a millimeter wave integrated circuit, and the capacitor is closer to a back end of the semiconductor die than a front end of the semiconductor die.”
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Liao discloses in Fig. 2, wherein the semiconductor die implements a millimeter wave integrated circuit (millimeter wave functionality disclosed in ¶ 0016, where 208 is the integrated chip, ¶ 0035, 0036), and the capacitor is closer to a back end of the semiconductor die than a front end of the semiconductor die (where chip 208 is the FEOL, the BEOL items are beginning at 210 and upward, where 204a/b, contain capacitors, ¶ 0033).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the semiconductor die implements a millimeter wave integrated circuit, and the capacitor is closer to a back end of the semiconductor die than a front end of the semiconductor die”, as disclosed by Liao in the system of Lisiansky, for the purpose of implementing larger elements such as capacitors in the build up layers of the interlevel metallization region. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lisiansky et al. (US 9,741,817) in view of Yang (US 9,876,068) in view of Lin et al. (US 2007/0267674).
Regarding claim 16, the prior art of Lisiansky et al. disclose the semiconductor die of claim 15, however Lisiansky does not specify,
“the first dielectric material associated with a first dielectric constant that is higher than a second dielectric constant associated with the second dielectric material.”
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Lin discloses in Fig. 1A,
the first dielectric material associated with a first dielectric constant that is higher than a second dielectric constant associated with the second dielectric material (142 is a high-k material and 130 is a low-k material).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“the first dielectric material associated with a first dielectric constant that is higher than a second dielectric constant associated with the second dielectric material.”, as disclosed by Lin in the system of Lisiansky, for the purpose of providing the appropriate materials for use as that of high-k material that performs well as a charge trapping material and separate interlevel dielectric insulator material which can mitigate RC delay due to the low-k characteristics . (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lisiansky et al. (US 9,741,817) in view of Yang (US 9,876,068) in view of Lin et al. (US 2021/0091169).
Regarding claim 17, the prior art of Lisiansky et al. disclose the semiconductor die of claim 15, however Lisiansky does not specify,
“further including a barrier layer between the second dielectric material and the metal protrusion.”
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Lin discloses in Figs. 1 and 2E, further including a barrier layer (104, “the capacitor interfacial layer 104 is a diffusion barrier for oxidants. Oxidants may, for example, be used during formation of the capacitor insulator layer 108. Absent the capacitor interfacial layer 104 being a diffusion barrier, oxidants could diffuse to the bottom electrode 106 and oxidize the top surface of the bottom electrode 106 during formation of the capacitor insulator layer 108.”, ¶ 0031) positioned between the dielectric material (108) and the metal protrusion (106).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further including a barrier layer between the second dielectric material and the metal protrusion”, as disclosed by Choi in the system of Lisiansky, for the purpose of preventing degradation of the bottom electrode with a barrier film. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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