DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 13 Mar 2026 for application number 18/320,816. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-20 are presented for examination. Elected claims 1-3, 7-10, and 13-14 are examined below; non-elected claims 4-6, 11-12, and 15-20 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to arguments towards the 103 rejection of claim 1, Applicant contends that the prior art does not teach, “a vertical channel…having first and second side surfaces opposite to teach other”, or “a plurality of word lines disposed on the first side surface…a plurality of back-gate electrodes disposed on the second side surface…”; Examiner respectfully disagrees.
Song teaches:
a vertical channel [vertical semiconductor pattern VSP; Fig. 28, para 0108] extending perpendicular to a top surface of a substrate [substrate SUB; Fig. 28, para 0096] and having first [first side; see annotated Fig. 28 below] and second side [second side; see annotated Fig. 28 below] surfaces opposite to each other [first and second sides are on opposite sides of VSP];
a plurality of word lines [word lines WL0-WLn; Fig. 28, para 0360] disposed on the first side surface [first side] of the vertical channel [VSP] and vertically stacked on the substrate [SUB];
a plurality of back-gate electrodes [gate electrodes EL1-3; Fig. 28, para 0098] disposed on the second side surface [second side] of the vertical channel [VSP] and vertically stacked on the substrate [SUB];
wherein the plurality of word lines [WL0-WLn] and the plurality of back-gate electrodes [EL1-3] extend along a first direction [D2; Fig. 28] parallel to the top surface of the substrate [SUB].
That is, Song teaches a first and second side that are on opposite sides of a vertical channel. As seen in Fig. 28, word lines exist on a first side, and back-gate electrodes exist on a second side. Further, the word lines and back-gate electrodes of Song extend in the D2 direction, which is parallel to the top surface of the substrate. Therefore, based on the current claim language, broadly and reasonably interpreted, the prior art teaches, “a vertical channel…having first and second side surfaces opposite to teach other”, or “a plurality of word lines disposed on the first side surface…a plurality of back-gate electrodes disposed on the second side surface…”
In response to arguments towards the 103 rejection of claim 9, Applicant contends that the prior art does not teach, “the first stack has a first sidewall…of the second stack”, or “a first stack disposed on a substrate…which are vertically stacked”; Examiner respectfully disagrees.
Song teaches:
a first stack [first stack; see annotated Fig. 28 above] disposed on a substrate [substrate SUB; Fig. 28, para 0096] and extending in a first direction [D2; Fig. 28], the first stack comprising a plurality of word lines [word lines WL0-WLn; Fig. 28, para 0360] which are vertically stacked;
a second stack [second stack; see annotated Fig. 28 above] disposed on the substrate [SUB] and extending in the first direction [D2], the second stack including a plurality of back-gate electrodes [gate electrodes EL1-3; Fig. 28, para 0098] which are vertically stacked;
wherein the first stack [first stack] has a first sidewall [for example, left side of first stack],
the second stack [second stack] has a second sidewall [for example, right side of second stack] facing the first sidewall [for example, left side of first stack] of the first stack [first stack], and
the plurality of vertical channels [VSP] are between the first sidewall [for example, left side of first stack] of the first stack [first stack] and the second sidewall [for example, right side of second stack] of the second stack [second stack].
That is, Song teaches first and second stacks with the claimed features, as well as the newly amended limitations of first and second stacks having sidewalls facing each other, with vertical channels between those sidewalls (see annotated Fig. 28 below). Therefore, based on the current claim language, broadly and reasonably interpreted, the prior art teaches, “the first stack has a first sidewall…of the second stack”, or “a first stack disposed on a substrate…which are vertically stacked.”
Regarding arguments to both claims 1 and 9, Applicant suggests, “that gate electrodes themselves correspond to word lines”; however, Song, paragraph 0099 merely provides that this may be the case. Fig. 28 clearly provides support that the word lines and gate electrodes are distinct elements in the structure. Further, the current claim language does not provide additional description of the distinction between the two. For these reasons, broadly and reasonably interpreting the current claim language, the prior art teaches the claim limitations of claims 1 and 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7-10, and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. [hereinafter as Song] (US 2024/0431103 A1 – relies on Foreign Application Priority Date of 01 Nov 2021) in view of Han et al. [hereinafter as Han] (US 2021/0175253 A1 – as cited in IDS filed 19 May 2023).
In reference to claim 1, Song teaches A semiconductor memory device, comprising:
a vertical channel [vertical semiconductor pattern VSP; Fig. 28, para 0108] extending perpendicular to a top surface of a substrate [substrate SUB; Fig. 28, para 0096] and having first [first side; see annotated Fig. 28 below] and second side [second side; see annotated Fig. 28 below] surfaces opposite to each other [first and second sides are on opposite sides of VSP];
a plurality of word lines [word lines WL0-WLn; Fig. 28, para 0360] disposed on the first side surface [first side] of the vertical channel [VSP] and vertically stacked on the substrate [SUB];
a plurality of back-gate electrodes [gate electrodes EL1-3; Fig. 28, para 0098] disposed on the second side surface [second side] of the vertical channel [VSP] and vertically stacked on the substrate [SUB];
a ferroelectric layer [data storage pattern DSP; Fig. 28, para 0108-0109 disclose that the DSP may be a ferroelectric layer] disposed between the word lines [WL0-WLn] and the vertical channel [VSP];
wherein the plurality of word lines [WL0-WLn] and the plurality of back-gate electrodes [EL1-3] extend along a first direction [D2; Fig. 28] parallel to the top surface of the substrate [SUB].
However, Song does not explicitly teach:
a first intermediate insulating layer disposed between the ferroelectric layer and the vertical channel; and
a second intermediate insulating layer disposed between the plurality of back-gate electrodes and the vertical channel.
Song and Han teach:
a first intermediate insulating layer [first interfacial insulation layer 332; Fig. 8, para 0094 of Han] disposed between the ferroelectric layer [first/second ferroelectric layer 312/314; Fig. 8, para 0040 of Han; analogously, DSP of Song] and the vertical channel [first/second channel layers 322/324; Fig. 8, para 0040 of Han; analogously, VSP of Song]; and
a second intermediate insulating layer [second interfacial insulation layer 334; Fig. 8, para 0096 of Han] disposed between [there would be an insulating layer on either side of the channel, one disposed between the channel and the word lines, and one disposed between the channel and the back gate electrodes] the plurality of back-gate electrodes [EL1-3 of Song] and the vertical channel [322/324 of Han; VSP of Song].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Song and Han before the effective filing date of the claimed invention, to include the insulating layers as disclosed by Han into the semiconductor device of Song in order to obtain a semiconductor device with an insulating layer between a ferroelectric layer and channel.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with an insulating layer between a ferroelectric layer and channel the predictable result of providing an improved device by preventing defect sites from being generated at an interface between a ferroelectric layer and a channel layer [Han, para 0095].
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In reference to claim 3, Song and Han teach the invention of claim 2.
Song teaches The semiconductor memory device of claim 2, further comprising a plurality of insulating isolation patterns [insulating spacers SP; para 0137] disposed between the plurality of word lines [WL0-WLn] and the plurality of back-gate electrodes [EL1-3], wherein the plurality of insulating isolation patterns [SP] are spaced apart [since SP are between the stack structure ST, they would be spaced apart in the D2 direction; paras 0135-0137] from one another in the first direction [D2], and wherein the vertical channel [VSP] is disposed between [SP separate the stacks; paras 0135-0137] a first insulating isolation pattern [a first one of SP] of the plurality of insulating isolation patterns [SP] and a second insulating isolation pattern [a second one of SP] of the plurality of insulating isolation patterns [SP].
In reference to claim 7, Song and Han teach the invention of claim 1.
Song teaches The semiconductor memory device of claim 1, wherein the plurality of word lines [WL0-WLn] and the plurality of back-gate electrodes [EL1-3] comprise the same conductive material [para 0100 discloses that the gate electrodes can be various conductive materials; para 0101 discloses that gate electrodes may correspond to word lines, i.e. they are the same material as the gate electrodes].
In reference to claim 8, Song and Han teach the invention of claim 1.
Song teaches The semiconductor memory device of claim 1, wherein the plurality of word lines [WL0-WLn] and the plurality of back-gate electrodes [EL1-3] comprise impurity-doped polysilicon [para 0100 discloses doped silicon; polysilicon is well-known to be a type of silicon that can be doped].
In reference to claim 9, Song teaches A semiconductor memory device, comprising:
a first stack [first stack; see annotated Fig. 28 above] disposed on a substrate [substrate SUB; Fig. 28, para 0096] and extending in a first direction [D2; Fig. 28], the first stack comprising a plurality of word lines [word lines WL0-WLn; Fig. 28, para 0360] which are vertically stacked;
a second stack [second stack; see annotated Fig. 28 above] disposed on the substrate [SUB] and extending in the first direction [D2], the second stack including a plurality of back-gate electrodes [gate electrodes EL1-3; Fig. 28, para 0098] which are vertically stacked;
a plurality of vertical channels [vertical semiconductor pattern VSP; Fig. 28, para 0108] between the first stack and the second stack, the plurality of vertical channels [VSP] spaced apart from one another in the first direction [D2];
a plurality of ferroelectric layers [data storage pattern DSP; see annotated Fig. 28 above, para 0108-0109 disclose that the DSP may be a ferroelectric layer] disposed between the plurality of vertical channels [VSP] and the first stack [first stack];
wherein the first stack [first stack] has a first sidewall [for example, left side of first stack],
the second stack [second stack] has a second sidewall [for example, right side of second stack] facing the first sidewall [for example, left side of first stack] of the first stack [first stack], and
the plurality of vertical channels [VSP] are between the first sidewall [for example, left side of first stack] of the first stack [first stack] and the second sidewall [for example, right side of second stack] of the second stack [second stack].
However, Song does not explicitly teach:
a plurality of first intermediate insulating layers disposed between the ferroelectric layer and the plurality of vertical channels; and
a plurality of second intermediate insulating layers disposed between the plurality of vertical channels and the second stack.
Song and Han teach:
a plurality of first intermediate insulating layers [first interfacial insulation layer 332; Fig. 8, para 0094 of Han] disposed between the ferroelectric layer [first/second ferroelectric layer 312/314; Fig. 8, para 0040 of Han; analogously, DSP of Song] and the plurality of vertical channels [first/second channel layers 322/324; Fig. 8, para 0040 of Han; analogously, VSP of Song]; and
a plurality of second intermediate insulating layers [second interfacial insulation layer 334; Fig. 8, para 0096 of Han] disposed between [there would be an insulating layer on either side of the channel, one disposed between the channel and the word lines, and one disposed between the channel and the back gate electrodes] the plurality of vertical channels [322/324 of Han; VSP of Song] and the second stack [second stack of Song].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Song and Han before the effective filing date of the claimed invention, to include the insulating layers as disclosed by Han into the semiconductor device of Song in order to obtain a semiconductor device with an insulating layer between a ferroelectric layer and channel.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with an insulating layer between a ferroelectric layer and channel the predictable result of providing an improved device by preventing defect sites from being generated at an interface between a ferroelectric layer and a channel layer [Han, para 0095].
In reference to claim 10, Song and Han teach the invention of claim 9.
Song and Han teach The semiconductor memory device of claim 9, further comprising a plurality of second ferroelectric layers [DSP of Song; see annotated Fig. 28 above] disposed between [there would be a ferroelectric layer between the second stack of gate electrodes and an insulating layer on that side of the channel] the second stack [second stack of Song] and the second intermediate insulating layers [334 of Han].
In reference to claim 13, Song and Han teach the invention of claim 9.
Song teaches The semiconductor memory device of claim 9, further comprising insulating isolation patterns [insulating spacers SP; para 0137] disposed between [since SP are between the stack structure ST, they would be spaced apart in the D2 direction; SP separate the stacks, and thus the vertical channels; paras 0135-0137] adjacent vertical channels [VSP] of the plurality of vertical channels [VSP] in the first direction [D2].
In reference to claim 14, Song and Han teach the invention of claim 9.
Song teaches The semiconductor memory device of claim 9, further comprising a plurality of bit lines [bit line BL; Fig. 28, para 0139] extending in a second direction [Fig. 1 discloses word lines running in one direction, and bit lines running in another direction; para 0085-0092] to cross the first stack [first stack] and the second stack [second stack], wherein the plurality of vertical channels [VSP] are disposed between the plurality of bit lines [BL] and the substrate [SUB] and are connected [VSP is connected to BL and SUB] to the plurality of bit lines [BL] and to the substrate [SUB].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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