Prosecution Insights
Last updated: April 19, 2026
Application No. 18/320,955

CHIP HEAT DISSIPATING STRUCTURE, PROCESS AND SEMICONDUCTOR DEVICE

Final Rejection §103§112
Filed
May 19, 2023
Examiner
LEE, EUGENE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hefei Smat Technology Co. Ltd.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
2y 9m
To Grant
87%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
728 granted / 891 resolved
+13.7% vs TC avg
Minimal +5% lift
Without
With
+4.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
930
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
41.1%
+1.1% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
24.5%
-15.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 891 resolved cases

Office Action

§103 §112
DETAILED ACTION Claim Objections Claim 1 is objected to because of the following informalities: in line 12, there is a typographical error in the limitation “a electric connection.” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 thru 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the packaging layer" in line 10. There is insufficient antecedent basis for this limitation in the claim. In line 12 of claim 1, the applicant states “a electric connection”; however, it is unclear whether the “electric connection” is a further description of “an output pin” stated in line 3 or the electric connection and output pin are completely different, separate structures. Appropriate clarification and/or correction are required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In view of the 112 rejection above, claim(s) 1 thru 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Edwards US 2008/0122061 A1. Edwards discloses (see, for example, FIG. 2, and 1B) a chip heat dissipating structure comprising at least a chip 101, package layer 102, bonding pad 144, output pin 120, heat fin 260, intermediate heat conductive layer 143, heat conductive protrusion 231, upper packaging layer 103, lower packaging layer 104, and electric connection 120. In FIG. 2, Edwards discloses the heat conductive protrusion 231 being symmetrical to the electrical connection 120. In paragraphs [0019], and [0027], Edwards discloses the metal layers 143, 144, 260 being heat spreaders, which dissipate heat from the chip 101. Edwards does not clearly disclose the heat fin 260 being on a whole surface of a side of the package layer; however, it would have been obvious to one of ordinary skill in the art to have the heat fin being on a whole surface of a side of the package layer in order to maximize the surface area of the heat fin, thereby letting heat dissipate evenly across the entire structure. Regarding claim 2, see, for example, FIG. 2 wherein Edwards discloses the intermediate structure 143 connects a back surface of the chip 101 with the heat fin 260. Regarding claim 3, see, for example, FIG. 2, and claim 6 wherein Edwards discloses he intermediate heat conductive layer 143 being arranged on the back surface of the chip 101 and an outer surface of the package layer 102 coplanar to the back surface of the chip 101, and a material of the intermediate heat conductive layer being copper. Regarding claim 4, see, for example, FIG. 2 wherein Edwards discloses each of the at least one heat conductive protrusion 231 being arranged on a side, which is located away from the chip 101, of the intermediate heat conductive layer 143, and each of the at least one heat conductive protrusion 231 has a shape of a regular cylinder or regular and is set obliquely or vertically on a surface of the intermediate heat conductive layer 143. Regarding claim 5, see, for example, FIG. 2 wherein Edwards discloses an end, which is located away from the intermediate heat conductive layer 143, of each of the at least one heat conductive protrusion 143 being connected to the heat fin 260. Regarding claims 6, the limitation "formed by electroplating or sputtering” is a product by process limitation that merely recites a process of forming a final product, and do not add any structural limitations to the final product. Regarding claim 8, see, for example, abstract wherein Edwards discloses a semiconductor chip, which is a semiconductor device. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Edwards US 2008/0122061 A1 as applied to claims 1-6 and 8 above, and further in view of Chung et US 9,984,983 B2. Edwards does not disclose a side wall fin is provided on one side wall, or each of two, three, or four side walls of the package layer, and each side wall fin is respectively connected to the bottom heat fin and the intermediate heat conductive layer. However, Chung discloses (see, for example, FIG. 1A) a sidewall fin 24 that covers a sidewall 162 of a package layer 16. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a side wall fin being provided on one side wall, or each of two, three, or four side walls of the package layer, and each side wall fin being respectively connected to the bottom heat fin and the intermediate heat conductive layer in order to insulate and protect the entire package layer, and also to further increase the heat dissipation surface area Response to Arguments Applicant’s arguments with respect to claim(s) 1-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee March 12, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

May 19, 2023
Application Filed
Oct 08, 2025
Non-Final Rejection — §103, §112
Jan 07, 2026
Response Filed
Mar 18, 2026
Final Rejection — §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
87%
With Interview (+4.9%)
2y 9m
Median Time to Grant
Moderate
PTA Risk
Based on 891 resolved cases by this examiner. Grant probability derived from career allow rate.

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