DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-10, 12-17, 20, and 25-28 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-10, 12-17, and 35 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naito (US PGPub 2018/0138299).
Re claim 1: Naito teaches (e.g. figs. 14 and 15) a semiconductor device comprising: a drift region (lightly doped n-type drift region 18; e.g. paragraph 106) of a first conductivity type (n-type) which is provided in a semiconductor substrate (10); a buffer region (buffer region 20; e.g. paragraph 111) of the first conductivity type (n-type impurities; e.g. paragraph 111) which is provided in a back surface (lower surface of 10; hereinafter “BS”) side of the semiconductor substrate (10) relative to the drift region (18) and which includes a first peak (20-1 as shown in fig. 15) of a doping concentration and a second peak (20-2 as shown in fig. 15) of the doping concentration, wherein the second peak (20-2) is provided in a front surface (upper surface of 10; hereinafter “FS”) side of the semiconductor substrate (10) relative to the first peak (20-1); a first lifetime control region (lifetime control region 88; e.g. paragraph 212) provided between the first peak (20-1) and the second peak (20-2) in a depth direction of the semiconductor substrate (10); and a collector region (P+-type collector region 22; e.g. paragraph 111) of a second conductivity type (p-type) which is provided at the back surface (BS) side of the semiconductor substrate (10), wherein the first peak (20-1) is a closest peak to the collector region (22) in the buffer region (20), and wherein the second peak (20-2) is a next closest peak to the collector region (22) in the buffer region (20).
Re claim 5: Naito teaches the semiconductor device according to claim 1, wherein the first lifetime control region (88) is away from the second peak (20-2) towards the back surface (BS) side by 0.5 µm or more (buffer regions are known to be approximately 35µm, therefore each peak (4µm wide thicknesses) 20-1 and 20-2 are 14µm apart, and distance between 20-2 and 88 (6 µm between each 20-x) would be approximately 5µm as shown in fig. 15) in the depth direction of the semiconductor substrate (10).
Re claim 6: Naito teaches the semiconductor device according to claim 1, wherein the first lifetime control region (88) is away from the first peak (20-1) towards the front surface (FS) side by 1.0 µm or more (floating regions 84 are 1 μm in the depth direction, therefore the middle of 88 would be approximately 2.5µm as shown in fig. 15 from the back surface of 10) in the depth direction of the semiconductor substrate (10).
Re claim 7: Naito teaches the semiconductor device according to claim 1, wherein the first peak (20-1) is provided at a depth of 0.5 µm or more and 2.0 µm or less (floating regions 84 are 1 μm in the depth direction, therefore the middle of 20-1 would be approximately 2.25µm as shown in fig. 15 from the back surface of 10) from a back surface (BS) of the semiconductor substrate (10).
Re claim 8: Naito teaches the semiconductor device according to claim 1, wherein the second peak (20-2) is provided at a depth of 2.0 µm or more (floating regions 84 are 0.75 μm in the depth direction, therefore the middle of 20-2 would be approximately 3.5µm as shown in fig. 15 from the back surface of 10) and 7.0 µm or less from a back surface (BS) of the semiconductor substrate (10).
Re claim 9: Naito teaches the semiconductor device according to claim 1, wherein a distance between the second peak (20-2) and a peak of a lifetime killer concentration (88) of the first lifetime control region (88) is 0.2 µm or more (floating regions 84 are 0.75 μm in the depth direction, therefore the middle of 88 would be approximately 2.5µm as shown in fig. 15 from the back surface of 10) in the depth direction of the semiconductor substrate (10).
Re claim 10: Naito teaches the semiconductor device according to claim 1, wherein a distance between the second peak (20-2) and a peak of a doping concentration (88) of the first lifetime control region (88) is smaller than a distance between an upper end of the collector region (22) and the peak of the first lifetime control region (88) in the depth direction of the semiconductor substrate (10).
Re claim 12: Naito teaches the semiconductor device according to claim 10, wherein the distance between the upper end of the collector region (22) and the peak of the first lifetime control region (88) is 0.1 µm or more (floating regions 84 are 0.75 μm in the depth direction, therefore the middle of 88 would be approximately 2.25µm as shown in fig. 15 from the back surface of 10) in the depth direction of the semiconductor substrate (10).
Re claim 13: Naito teaches the semiconductor device according to claim 10, wherein a doping concentration at the peak (88) of the first lifetime control region (88) is larger than a doping concentration at the first peak (20-1) and smaller than a doping concentration at a peak of the collector region (peak of 22). The Examiner is taking official notice that these doping concentration would be known, as evidenced by the prior art used in the previous Office Action.
Re claim 14: Naito teaches the semiconductor device according to claim 10, wherein a doping concentration at a peak of the collector region is 1.0 E17 cm-3 or more and 1.0 E19 cm-3 or less (P+ collector region 22; e.g. paragraph 111).
Re claim 15: Naito teaches the semiconductor device according to claim 1, wherein a doping concentration at a peak of the first lifetime control region (88) is 1.0 E15 cm-3 or more and 1.0 E17 cm-3 or less. The Examiner is taking official notice that these doping concentration would be known, as evidenced by the prior art used in the previous Office Action.
Re claim 16: Naito teaches the semiconductor device according to claim 1, wherein a full width at half maximum of a peak of a doping concentration of the first lifetime control region (88) is 0.5 µm or less. The Examiner is taking official notice that the FWHM of the lifetime control region would be known, as evidenced by the prior art used in the previous Office Action.
Re claim 17: Naito teaches the semiconductor device according to claim 1, comprising: a transistor portion (IGBT portion 70; e.g. paragraph 79) and a diode portion (FWD portion 90; e.g. paragraph 79) which are provided in the semiconductor substrate (10).
Re claim 35: Naito teaches (e.g. figs. 14 and 15) a semiconductor device comprising: a drift region (lightly doped n-type drift region 18; e.g. paragraph 106) of a first conductivity type (n-type) which is provided in a semiconductor substrate (10); a buffer region (buffer region 20; e.g. paragraph 111) of the first conductivity type (n-type impurities; e.g. paragraph 111) which is provided in a back surface (lower surface of 10; hereinafter “BS”) side of the semiconductor substrate (10) relative to the drift region (18) and which includes a first peak (20-1 as shown in fig. 15) of a doping concentration and a second peak (20-2 as shown in fig. 15) of the doping concentration, wherein the second peak (20-2) is provided in a front surface (upper surface of 10; hereinafter “FS”) side of the semiconductor substrate (10) relative to the first peak (20-1); and a first lifetime control region (lifetime control region 88; e.g. paragraph 212) provided between the first peak (20-1) and the second peak (20-2) in a depth direction of the semiconductor substrate (10), wherein the second peak (20-2) is provided at a depth of 2.0 µm or more (floating regions 84 are 0.75 μm in the depth direction, therefore the middle of 20-2 would be approximately 3.5µm as shown in fig. 15 from the back surface of 10) and 7.0 µm or less from the back surface (BS) of the semiconductor substrate (10).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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