DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13, 18, and 20 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13, 18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murakawa et al. (US PGPub 2019/0252534; hereinafter “Murakawa”) in view of Naito (US PGPub 2018/0350962) and Miyata et al. (US PGPub 2019/0097030; hereinafter “Miyata”).
Re claim 1: Murakawa teaches (e.g. figs. 6, 3A, and 3B) a semiconductor device that includes a transistor portion (regions 1a and 1c; e.g. paragraph 47; hereinafter “TP”) and a diode portion (region of 1b; hereinafter “DP”), the semiconductor device comprising: a drift region (N--type drift layer 11; e.g. paragraph 26) of a first conductivity type (N--type region) provided in a semiconductor substrate (10); a base region (12a, 12b; 12b having a lower concentration of p-type dopants; e.g. paragraph 40) of a second conductivity type (p-type) provided above the drift region (11); emitter regions (emitter 14; e.g. paragraph 31) of the first conductivity type (N+ type region) which are provided above the base region (12a, 12b) and which have a doping concentration higher than that of the drift region (11); contact regions (15c, 15a) of the second conductivity type (P-type region) which are provided above the base region (12a, 12b) and which have a doping concentration higher (p-type region 15c has higher concentration than p--type region of 12b) than that of the base region (12a, 12b); and a plurality of trench portions (trench 13; e.g. paragraph 41) provided at a front surface (upper surface of 10) of the semiconductor substrate (10), wherein the transistor portion (TP) has a boundary region (1c) provided to be adjacent to the diode portion (DP), and the contact regions (15c) and the base region (12a, 12b) are alternately arranged in the extension direction (direction which trenches 13 extends; hereinafter “ED”), at the front surface in the boundary region (1c) such that each of the contact regions (15c) is separated from a nearest neighboring one of the contact regions (15c) by the base region (12b) in the extension direction (ED) at the front surface in the boundary region (1c).
Murakawa is silent as to explicitly teaching a lifetime control region is provided from the diode portion, across the boundary region, to the transistor portion provided with the emitter regions, in an array direction of the plurality of trench portions; and the boundary region has a plug region of the second conductivity type which is provided to extend in an extension direction of the plurality of trench portions and which has a doping concentration higher than that of the base region.
Naito teaches (e.g. figs. 1, 2) a lifetime control region (lifetime killer 36; e.g. paragraph 66) is provided from the diode portion (portion of 80 over 82 of fig. 2), across the boundary region (portion of 80 between right 82 and left 22 of fig. 2), to the transistor portion (70) provided with the emitter regions (12), in an array direction (left-right direction of fig. 2) of the plurality of trench portions (40, 30).
Miyata teaches (e.g. figs. 1-3) the boundary region (furthest left unit cell of 22 as shown in fig. 3) has a plug region (P++ region 7b; hereinafter “PRB”) of the second conductivity type (P++-type region) which is provided to extend in an extension direction (up-down direction of fig. 1) of the plurality of trench portions (2) and which has a doping concentration higher than that of the base region (5).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the lifetime killer region as taught by Naito and to use the highly doped plug region as taught by Miyata in the device of Murakawa in order to have the predictable result of improve recovery characteristics of the diode (see paragraph 66 of Naito) and in order to have the predictable result of using a highly doped region where contact plugs make connection to the semiconductor to improve ohmic contact between elements and reduce unwanted parasitic Schottky contacts, respectively.
Re claim 2: Murakawa teaches the semiconductor device according to claim 1, wherein the boundary region (1c of Murakawa) is constituted by one mesa portion (region between two adjacent trenches 13 of Murakawa) provided to be interposed between two trench portions (13) among the plurality of trench portions (13).
Re claim 3: Murakawa teaches the semiconductor device according to claim 1, wherein in the transistor portion (TP) other than the boundary region (1c), the contact regions (15a) and the emitter regions (14) are alternately arranged in the extension direction (ED), and each of the contact regions (15c) in the boundary region (1c) is provided for a position in the extension direction (ED) to correspond to that of a corresponding one of the contact regions (15a) in the transistor portion (TP) other than the boundary region (1c).
Re claim 4: Murakawa teaches the semiconductor device according to claim 1, wherein in the boundary region (1c), a thinning rate which is a rate of the base region (12a, 12b) exposed on the front surface, is 30% or more and 80% or less (approximately 75% of the front surface is the base region 12a, 12b).
Re claim 5: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 1, wherein in the boundary region (1c), a length of the plug region (17 of Miyata extends along the entire mesa structure) which extends in the extension direction (ED of Murakawa) is longer than a length in the extension direction of the contact regions (15a, 15c of Murakawa) as arranged in the extension direction (ED of Murakawa).
Re claim 6: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 1, wherein the diode portion (DP) includes at least one mesa portion adjacent the boundary region (1c), the at least one mesa portion of the diode portion (DP) has a plug region (region of 1b exposed by openings in 18 of Murakawa provided with 7b of Miyata; hereinafter “PRD”), the plug region (PRD) of the at least one mesa portion of the diode portion (DP) is in contact with the base region (12b of Murakawa/5 of Miyata), and the plug region (PRB) of the boundary region (1c) has a same doping concentration as the plug region (PRD) of the at least one mesa portion of the diode portion (DP).
Re claim 7: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 1, wherein the plurality of trench portions (13 of Murakawa) in the boundary region (1c of Murakawa) are dummy trench portions (gates in 1b are not connected to gate electrode voltages as shown in fig. 6).
Re claim 8: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 1, wherein the emitter regions (14) closest to the boundary region (1c) in the array direction is interposed between dummy trench portions (gates in 1b).
Re claim 9: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 2, wherein the emitter regions (14) closest to the boundary region (1c) in the array direction is interposed between dummy trench portions (gates in 1b).
Re claim 10: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 1, wherein the boundary region (1c) is not provided with the emitter regions (14).
Re claim 11: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 2, wherein the boundary region (1c) is not provided with the emitter regions (14).
Re claim 12: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 1, comprising: a collector region (21) of the second conductivity type (P+ - type region 21) provided on a back surface of the semiconductor substrate (10), below the boundary region (1c).
Re claim 13: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 2, comprising: a collector region (21) of the second conductivity type (P+ - type region 21) provided on a back surface of the semiconductor substrate (10), below the boundary region (1c).
Re claim 18: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 1, wherein the transistor portion (TP) has an accumulation region (16) of the first conductivity type (N+ - type region 16 of Naito) which is provided above the drift region (11) and which has a doping concentration higher than that of the drift region (11); and the accumulation regions (16 of Naito) are provided in both of the boundary region (1c) and the transistor portion (TP) other than the boundary region (1c).
Re claim 20: Murakawa in view of Naito and Miyata teaches the semiconductor device according to claim 2, wherein the transistor portion (TP) has an accumulation region (16) of the first conductivity type (N+ - type region 16 of Naito) which is provided above the drift region (11) and which has a doping concentration higher than that of the drift region (11); and the accumulation regions (16 of Naito) are provided in both of the boundary region (1c) and the transistor portion (TP) other than the boundary region (1c).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
Prosecution Insights