DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device embodiment 4 as shown in fig. 4 (claims 1-11, 18, and 20 readable thereon, claims 12-17, and 19 withdrawn) in the reply filed on 12/3/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13, 18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US PGPub 2018/0350962) in view of Miyata et al. (US PGPub 2019/0097030; hereinafter “Miyata”).
Re claim 1: Naito teaches (e.g. figs. 1, 2, and labeled fig. 1 below) a semiconductor device that includes a transistor portion (region 22 of 70 and 22 which extends into 80; e.g. paragraph 47; hereinafter “TP”) and a diode portion (region to the right of TP of fig. 2; hereinafter “DP”), the semiconductor device comprising: a drift region (18) of a first conductivity type (N--type region) provided in a semiconductor substrate (10); a base region (14) of a second conductivity type (p-type) provided above the drift region (18); an emitter region (12) of the first conductivity type (N+ type region) which is provided above the base region (14) and which has a doping concentration higher than that of the drift region (18); a contact region (15 in 70 and regions of 15 in 80 adjacent to 15 but not adjacent to emitters 12; hereinafter “CR” as labeled below) of the second conductivity type (P+-type region) which is provided above the base region (14) and which has a doping concentration higher than that of the base region (14); and a plurality of trench portions (gate trench portions 40 and 30; e.g. paragraph 41) provided at a front surface (upper surface of 10) of the semiconductor substrate (10), wherein the transistor portion (TP) has a boundary region (furthest right mesa of TP of fig. 2; hereinafter “BR”) provided to be adjacent to the diode portion (DP), a lifetime control region (36) is provided from the diode portion (DP), across the boundary region (BR), to the transistor portion (TP) provided with the emitter region (12), in an array direction (left-right direction of fig. 2) of the plurality of trench portions (40, 30), and the contact region (CR) and the base region (14) are alternately arranged in the extension direction (up-down direction of fig. 1), at the front surface in the boundary region (BR).
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Naito is silent as to explicitly teaching the boundary region has a plug region of the second conductivity type which is provided to extend in an extension direction of the plurality of trench portions and which has a doping concentration higher than that of the base region.
Miyata teaches (e.g. figs. 1-3) the boundary region (furthest left unit cell of 22 as shown in fig. 3) has a plug region (P++ region 17) of the second conductivity type (P++-type region) which is provided to extend in an extension direction (up-down direction of fig. 1) of the plurality of trench portions (2) and which has a doping concentration higher than that of the base region (5).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the highly doped plug region as taught by Miyata in the device of Naito in order to have the predictable result of using a highly doped region where contact plugs make connection to the semiconductor to improve ohmic contact between elements and reduce unwanted parasitic Schottky contacts.
Re claim 2: Naito teaches the semiconductor device according to claim 1, wherein the boundary region (BR) is constituted by one mesa portion provided to be interposed between two trench portions (BR is provided between two 30) among the plurality of trench portions (30, 40).
Re claim 3: Naito teaches the semiconductor device according to claim 1, wherein in the transistor portion (TP) other than the boundary region (BR), the contact region (15 in 70) and the emitter region (12) are alternately arranged in the extension direction (up-down direction of fig. 1), and the contact region (CR) in the boundary region (BR) is provided for a position in the extension direction (up-down direction of fig. 1) to correspond to that of the contact region (15 in 70) in the transistor portion (TP) other than the boundary region (BR).
Re claim 4: Naito teaches the semiconductor device according to claim 1, wherein in the boundary region (BR), a thinning rate which is a rate of the base region (14) exposed (presumably all surfaces of the device is passivated and is not exposed) on the front surface, is 30% or more and 80% or less.
Re claim 5: Naito in view of Miyata teaches the semiconductor device according to claim 1, wherein in the boundary region (BR), a length of the plug region (17 of Miyata extends along the entire mesa structure) which extends in the extension direction (up-down direction of fig. 1 of Miyata) is longer than a length of the contact region (CR of Naito) which extends in the extension direction (up-down direction of fig. 1 of Naito).
Re claim 6: Naito in view of Miyata teaches the semiconductor device according to claim 1, wherein the diode portion (22 of Miyata) has the plug region (7b of Miyata), and the plug region (17 of Miyata) of the boundary region (BR of Naito) has a same doping concentration as the plug region (7b of Miyata) of the diode portion (22 of Miyata).
Re claim 7: Naito teaches the semiconductor device according to claim 1, wherein the plurality of trench portions (40, 30 of Naito) in the boundary region (BR of Naito) are dummy trench portions (dummy trenches 30).
Re claim 8: Naito teaches the semiconductor device according to claim 1, wherein the emitter region (12) closest to the boundary region (BR) in the array direction is interposed between dummy trench portions (dummy trenches 30).
Re claim 9: Naito teaches the semiconductor device according to claim 2, wherein the emitter region (12) closest to the boundary region (BR) in the array direction is interposed between dummy trench portions (dummy trenches 30).
Re claim 10: Naito teaches the semiconductor device according to claim 1, wherein the boundary region (BR) is not provided with the emitter region (no 12 are in BR).
Re claim 11: Naito teaches the semiconductor device according to claim 2, wherein the boundary region (BR) is not provided with the emitter region (no 12 are in BR).
Re claim 12: Naito teaches the semiconductor device according to claim 1, comprising: a collector region (22) of the second conductivity type (P+ - type region 22) provided on a back surface of the semiconductor substrate (10), below the boundary region (BR).
Re claim 13: Naito teaches the semiconductor device according to claim 2, comprising: a collector region (22) of the second conductivity type (P+ - type region 22) provided on a back surface of the semiconductor substrate (10), below the boundary region (BR).
Re claim 18: Naito teaches the semiconductor device according to claim 1, wherein the transistor portion (TP) has an accumulation region (16) of the first conductivity type (N+ - type region 16) which is provided above the drift region (18) and which has a doping concentration higher than that of the drift region (18); and the accumulation regions (16) are provided in both of the boundary region (BR) and the transistor portion (TP) other than the boundary region.
Re claim 20: Naito teaches the semiconductor device according to claim 2, wherein the transistor portion (TP) has an accumulation region (16) of the first conductivity type (N+ - type region 16) which is provided above the drift region (18) and which has a doping concentration higher than that of the drift region (18); and the accumulation regions (16) are provided in both of the boundary region (BR) and the transistor portion (TP) other than the boundary region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898