Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Claim(s) 1-5, 11-12, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al., U.S. Patent 10,388,732 in view of Seol et al., US 2022/0077321.
Frougier et al. shows the invention as claimed including a semiconductor device comprising:
At least one first two-dimensional material layer 44;
A source electrode and a drain electrode 52 that are respectively on both sides of the at least one first two-dimensional material layer;
Second two-dimensional material layers 46 respectively on a side of the source electrode and a side of the drain electrode and connected to the at least one first two-dimensional material layer;
A gate insulating layer 37 surrounding the at least one first two-dimensional material layer; and
A gate electrode 39 on the gate insulating layer (see, for example, figs. 6-11 and col. 4-line 58 to col. 8-line 3).
Frougier et al. does not expressly disclose wherein a number of layers in the second two-dimensional material layers is different from a number of layers in the at least one first two-dimensional material layer. Seol et al. discloses wherein a number of layers in the second two-dimensional material layers is different from a number of layers in the at least one first two-dimensional material layer (see paragraphs 0062-0067). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Frougier et al. so as to comprise the claimed two-dimensional material configuration of Seol et al. because in such a way the properties of the electrical device can be further optimized.
Concerning dependent claim 2, note that Frougier et al. discloses wherein the second two-dimensional material layers extend in a direction substantially perpendicular to the at least one first two-dimensional material layer (see fig. 9).
With respect to dependent claim 3, note that Frougier et al. discloses wherein the second two-dimensional material layers 46 are in planar contact with the source electrode and the drain electrode (see fig. 10).
Regarding dependent claim 4, note that Frougier et al. discloses wherein: the at least one first two-dimensional material layer comprises a plurality of first two-dimensional material layers, the plurality of first two-dimensional material layers extends in a direction substantially perpendicular to the second two-dimensional material layers, and the plurality of first two-dimensional material layers are spaced apart from each other (see fig. 11).
With respect to dependent claim 6, note that the at least one first two-dimensional material layer comprises a two-dimensional material having semiconductor characteristics (see col. 6-lines 48-63).
As to dependent claims 7-8, note that the at least one first two-dimensional material layer comprises a material having the claimed bandgap and can be a transition metal dichalcogenide (see col. 6-lines 10-31).
Concerning dependent claim 9, note that Frougier et al. discloses wherein the second two-dimensional material layers comprise a two-dimensional material having semiconductor characteristics (see col. 6-lines 32-46).
With respect to dependent claim 10, note that Frougier et al. discloses wherein the second two-dimensional material layers comprise a TMD (see col. 6-lines 10-46).
Regarding dependent claim 11, note that the number of layers in the second two-dimensional material layers is equal to the number of layers in the first two-dimensional material layer (see fig. 11).
With respect to dependent claim 12, note that Frougier et al. can be considered to be an electronic apparatus.
As to independent claim 21, Frougier et al. shows the device substantially as claimed including a semiconductor device comprising:
At least one first two-dimensional material layer 44;
A source electrode and a drain electrode 52 that are respectively on both sides of the at least one first two-dimensional material layer;
Second two-dimensional material layers 46 respectively on a side of the source electrode and a side of the drain electrode and connected to the at least one first two-dimensional material layer;
A gate insulating layer 37 surrounding the at least one first two-dimensional material layer; and a gate electrode 39 on the gate insulating layer (see, for example, figs. 6-11 and col. 4-line 58 to col. 8-line 3).
Frougier et al. does not expressly disclose wherein the at least one first two-dimensional material layer has an electrical property different from the second two-dimensional material layers. Seol et al. discloses wherein different channel layers are composed of different two-dimensional material layers (see paragraph 0088) which means that at least one first two-dimensional material layer of one channel will be of a different material and have a different electrical property than the second two-dimensional material layers. In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Frougier et al. so as to comprise the first and second two-dimensional material configuration of Seol et al. because having the material layers of different materials is shown to be suitable by Seol et al. and allows for different channel layers to have their properties optimized individually.
Concerning dependent claim 22, note that in Frougier et al. the at least one first two-dimensional material layer and the second two-dimensional material layers comprise a transition metal dichalcogenide and a dopant (see, for example, paragraphs 0066,0087
With respect to dependent claim 23, note that in Frougier et al. the channel region MAY be doped which covers an embodiment where the first two-dimensional layer does not comprise the dopant.
As per dependent claim 24, note that, as stated above with respect to Frougier et al., the channels of the two-dimensional material layers can consist of different materials.
Concerning dependent claim 25, note that Frougier et al. discloses the channel formed of the claimed materials.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 11-12, and 21-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
April 20, 2026