DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on Sep. 29th 2025 is acknowledged. The traversal is on the grounds that the claimed separate inventions have not acquired a separate status in the art and the search and examination of all the claims in an application would not be unduly burdened on the Examiner. This is not found persuasive because the inventions are distinct if either or both of the following can be shown: (1) that the process claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP 806.05 (f)). Here the product as claim 1 can be made by another and materially different process, such as a method that select forming the upper barrier layer and the gate semiconductor layer instead of etching the upper barrier layer and the gate semiconductor layer after forming. Therefore, the inventions have independent or distinct features and require a separate status in the art. In addition, there is a search burden because the inventions have acquired a separate status in the art in view of their different classification; the invention have acquired a separate status in the art due to their recognized subject matter; or the invention require a different field of search (e.g. searching different classes/subclasses or electronic resources, or employing different search strategies or search queries); for example, classification and keyword search regarding method of manufacturing requires sequential steps, and/or particular process, not in the product. The restriction requirement between product and process of making has been maintained for above reason.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-19 are examined in this office action. Claim 20 is withdrawn from further consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 7-8 and 10 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (KR 20150091703), hereinafter Lee.
Regarding claim 1, Lee teaches a semiconductor device (nitride semiconductor device; Abstract) comprising:
a channel layer (fig. 6h, GaN channel layer 110; para. 0128);
a lower barrier layer (AlGaN barrier layer 120, lower cap layer 150; para. 0128, 0181) on the channel layer (110) and comprising first impurities (150 has a small amount dope; para. 0273);
an upper barrier layer (p-type gate layer 130; para. 0128) on the lower barrier layer (150, 120) and comprising second impurities (at least one of Mg, C; para. 0170) having a concentration (concentration of doping of 130) greater than (150 has a smaller amount than 130; para. 0273) a concentration of the first impurities (concentration of doping of 150);
a gate electrode (gate electrode 160; para. 0130) on the upper barrier layer (130);
a gate semiconductor layer (upper cap layer 140; para. 0128) between the upper barrier layer (130) and the gate electrode (160); and
a source (source electrode 170; para. 0132) and a drain (drain electrode 180) that are on the channel layer (110) and are spaced apart from each other.
Regarding claim 3, Lee further teaches the semiconductor device of claim 1, wherein each of the upper barrier layer (fig. 6h, 130 may be AlGaN; para. 0167) and the lower barrier layer (150, 120, 120 is AlGaN barrier) comprises AlGaN.
Regarding claim 5, Lee further teaches the semiconductor device of claim 1, wherein the lower barrier layer (fig. 6h, 150, 120 with the inject high-resistance GaN layer; para. 0138) exhibits semi-insulating characteristics (semi-insulating characteristics; para. 0138).
Regarding claim 7, Lee further teaches the semiconductor device of claim 1, wherein the channel layer (fig. 6, 110) comprises a group III-V compound semiconductor (110 is GaN).
Regarding claim 8, Lee further teaches the semiconductor device of claim 1, wherein the gate semiconductor layer (fig. 6, 140) comprises p-type GaN (p-type and GaN with Al, y=0; para. 0173).
Regarding claim 10, Lee further teaches the semiconductor device of claim 1, wherein the semiconductor device (nitride semiconductor device) comprises a high electron mobility transistor (HEMTs; para. 0003) having a normally off characteristic (normally-off device; para. 0045).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 6, Lee further teaches the semiconductor device of claim 1, wherein the second impurities (dope of 130) comprise magnesium (at least one of Mg, C; para. 0170).
Lee fails to explicitly teach the first impurities comprise carbon.
However, it would be obvious to configure the first impurities (smaller amount doping in 150) comprise carbon (150 is similar to 140, which doping is a p-type doped, which can be Mg and C; para. 0013, 0176, 0273).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first impurities comprise carbon.
Doing so would realize more simply process for doping and can improve gate current characteristics or breakdown voltage characteristics (para. 0207).
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hwang et al. (US 20120086049).
Regarding claim 2, Lee teaches the semiconductor device of claim 1 including the second impurities (at least one of Mg, C).
Lee fails to explicitly teach the second impurities are at shallower level with respect to a top of the upper barrier layer than a level of the first impurities with respect to a top of the lower barrier layer.
Hwang teaches the second impurities (Hwang: Mg; para. 0064) are at shallower level (Hwang: fig. 5B, the upper energy level decrease/shallower) with respect to a top of the upper barrier layer (Hwang: left side of second barrier layer 40; para. 0064, similar to 130 of Lee) than a level (Hwang: the upper energy level of maximum at the left side of first barrier layer 38; para. 0064, similar to 120, 150 of Lee) of the first impurities (Lee: smaller amount p-type dope) with respect to a top of the lower barrier layer (Hwang: left side of first barrier layer).
Hwang and Lee are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the second impurities are at shallower level with respect to a top of the upper barrier layer than a level of the first impurities with respect to a top of the lower barrier layer as taught by Hwang.
Doing so would realize a polarization density gradient for an enhancement mode (Hwang: para. 0008, 0063).
Regarding claim 4, Lee teaches the semiconductor device of claim 1, wherein the upper barrier layer (fig. 6h, 130) comprises AlxGaixN (130 may be AlGaN; para. 0167),
the lower barrier layer (120, 150) comprises AlyGaiyN (120 is AlGaN barrier).
Lee fails to explicitly teach x is less than the y.
However, Hwang teaches x (Hwang: fig. 1, content of Al of second barrier layer 40; para. 0064, similar to 130 of Lee) is less than (Hwang: content of Al of 40 decreases from 38; para. 0064) the y (Hwang: content of Al of first barrier layer 38; para. 0064, similar to 120, 150 of Lee).
Hwang and Lee are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add x is less than the y as taught by Hwang.
Doing so would realize a polarization density gradient for an enhancement mode (Hwang: para. 0008, 0063).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hikita et al. (US 20060273347).
Regarding claim 9, Lee teaches the semiconductor device of claim 1 including the lower barrier layer (fig. 6h, 120, 150), the upper barrier layer (130), the gate semiconductor layer (140), and the gate electrode (160).
Lee fails to explicitly teach a passivation layer surrounding the lower barrier layer, the upper barrier layer, the gate semiconductor layer, and the gate electrode.
However, Hikita teaches a passivation layer (Hikita: fig. 1, SiN film 108; para. 0034) surrounding the lower barrier layer (Hikita: AlGaN layer 104; para. 0034, similar to 120, 150 of Lee), the upper barrier layer (Hikita: p-type GaN layer 105; para. 0034, similar to 130 of Lee), the gate semiconductor layer (Hikita: p-type GaN layer 106; para. 0034, similar to 140 of Lee), and the gate electrode (Hikita: gate electrode 111; para. 0034, similar to 160 of Lee).
Hikita and Lee are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a passivation layer surrounding the lower barrier layer, the upper barrier layer, the gate semiconductor layer, and the gate electrode as taught by Hikita.
Doing so would realize a passive layer to suppress the generation of current collapse (Hikita: para. 0037).
Claim(s) 11-13, 15 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Sato et al. (US 20090212325).
Regarding claim 11, Lee teaches a semiconductor device (nitride semiconductor device; Abstract) comprising:
a channel layer (fig. 6h, GaN channel layer 110; para. 0128);
a lower barrier layer (AlGaN barrier layer 120, lower cap layer 150; para. 0128, 0181) on the channel layer (110) and comprising first impurities (150 has a small amount dope; para. 0273);
an upper barrier layer (p-type gate layer 130; para. 0128) on the lower barrier layer (150, 120) and comprising second impurities (at least one of Mg, C; para. 0170) having a concentration (concentration of doping of 130) greater than (150 has a smaller amount than 130; para. 0273) a concentration of the first impurities (concentration of doping of 150);
a gate electrode (gate electrode 160; para. 0130) on the upper barrier layer (130);
a gate semiconductor layer (upper cap layer 140; para. 0128) between the upper barrier layer (130) and the gate electrode (160); and
a source (source electrode 170; para. 0132) and a drain (drain electrode 180) that are on the channel layer (110) and are spaced apart from each other.
Lee fails to teach the lower barrier layer defines a recess, and a thickness of a portion of the lower barrier layer that is close to the gate electrode is less than a thickness of an edge portion of the lower barrier layer.
However, Sato teaches the lower barrier layer (Sato: fig. 5, electron supply layer 4; para. 0026, similar to 120, 150 of Lee) defines a recess (Sato: recess under p-type semiconductor layer 5; para. 0027), and a thickness of a portion (Sato: thickness of portion under 5) of the lower barrier layer (Sato: 4) that is close to the gate electrode (Sato: gate electrode 8; para. 0025, similar to 160 of Lee) is less than a thickness of an edge portion (Sato: thickness of edge portion) of the lower barrier layer (Sato: 4).
Sato and Lee are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the lower barrier layer defines a recess as taught by Sato.
Doing so would realize a gate structure to stabilize the characteristics and therefore improves a production yield (Sato: para. 0040).
Regarding claim 12, Lee in view of Sato further teaches the semiconductor device of claim 11, wherein a point where a thickness (Sato: fig. 5, thickness of portion under 5) of the lower barrier layer (Sato: 4) decreases is about 1 nm or more and about 1,000 nm or less (Sato: decrease 25-10=15 nm; para. 0032) in a direction (downward) away from the gate electrode (Sato: 8).
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 13, Lee in view of Sato further teaches the semiconductor device of claim 11, wherein the recess (Sato: fig. 5, recess under 5) has a depth of about 1 nm or more and about 20 nm or less (Sato: depth of 25-10=15 nm; para. 0032).
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 15, Lee further teaches the semiconductor device of claim 11, wherein each of the upper barrier layer (fig. 6h, 130 may be AlGaN; para. 0167) and the lower barrier layer (150, 120, 120 is AlGaN barrier) comprises AlGaN.
Regarding claim 17, Lee further teaches the semiconductor device of claim 11, wherein the lower barrier layer (fig. 6h, 150, 120 with the inject high-resistance GaN layer; para. 0138) exhibits semi-insulating characteristics (semi-insulating characteristics; para. 0138).
Regarding claim 18, Lee further teaches the semiconductor device of claim 11, wherein the second impurities (dope of 130) comprise magnesium (at least one of Mg, C; para. 0170).
Lee in view of Sato fails to explicitly teach the first impurities comprise carbon.
However, it would be obvious to configure the first impurities (smaller amount doping in 150) comprise carbon (150 is similar to 140, which doping is a p-type doped, which can be Mg and C same as 130; para. 0013, 0176, 0273).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first impurities comprise carbon.
Doing so would realize more simply process for doping and can improve gate current characteristics or breakdown voltage characteristics (para. 0207).
Regarding claim 19, Lee in view of Sato further teaches the semiconductor device of claim 11, further comprising:
a passivation layer (Sato: fig. 5, insulating film 7; para. 0042) surrounding (surrounding the stack of) the lower barrier layer (Sato: 4), the upper barrier layer (Sato: 5), the gate semiconductor layer (Sato: p-type semiconductor layer 6; para. 0042, similar to 140 of Lee), and the gate electrode (Sato: 8).
Claim(s) 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Sato as applied to claims 11 above, and further in view of Hwang.
Regarding claim 14, Lee teaches the semiconductor device of claim 11 including the second impurities (at least one of Mg, C).
Lee in view of Sato fails to explicitly teach the second impurities of the upper barrier layer are shallower with respect to a top of the upper barrier layer than a level of the first impurities with respect to a top of the lower barrier layer.
Hwang teaches the second impurities (Hwang: Mg; para. 0064) of the upper barrier layer are shallower (Hwang: fig. 5B, the upper energy level decrease/shallower at the left side of second barrier layer 40; para. 0064, similar to 130 of Lee) with respect to a top of the upper barrier layer (left side of second barrier layer) than a level (Hwang: the upper energy level of maximum at the left side of first barrier layer 38; para. 0064, similar to 120, 150 of Lee) of the first impurities (Lee: smaller amount p-type dope) with respect to a top of the lower barrier layer (Hwang: left side of first barrier layer).
Hwang, Sato and Lee are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the second impurities of the upper barrier layer are shallower with respect to a top of the upper barrier layer than a level of the first impurities with respect to a top of the lower barrier layer as taught by Hwang.
Doing so would realize a polarization density gradient for an enhancement mode (Hwang: para. 0008, 0063).
Regarding claim 16, Lee teaches the semiconductor device of claim 11 including an aluminum concentration of the upper barrier layer (fig. 6h, Al in 130 may be AlGaN; para. 0167).
Lee in view of Sato fails to teach an aluminum concentration of the upper barrier layer is less than an aluminum concentration of the lower barrier layer.
However, Hwang teaches an aluminum concentration of the upper barrier layer (Hwang: fig. 1, content of Al of second barrier layer 40; para. 0064, similar to 130 of Lee) is less than (Hwang: content of Al of 40 decreases from 38; para. 0064) an aluminum concentration of the lower barrier layer (Hwang: content of Al of first barrier layer 38; para. 0064, similar to 120, 150 of Lee).
Hwang, Sato and Lee are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an aluminum concentration of the upper barrier layer is less than an aluminum concentration of the lower barrier layer as taught by Hwang.
Doing so would realize a polarization density gradient for an enhancement mode (Hwang: para. 0008, 0063).
Conclusion
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/ZHIJUN XU/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 10/16/25