DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 10/10/2025, without traverse to prosecute the claims of Invention I, claims 1-16 is acknowledged.
The restriction filed 8/21/2025 had a clerical error and should have classified claims 1-15 as invention I and claims 16-20 as invention II. The examiner called Attorney Salzano at 202-756-1123 11/25/2025 and left a voicemail identifying the clerical error in the restriction.
For compact prosecution, the examiner is examining claims 1-15.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/22/2023, 2/21/2025, and 7/24/2025 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 7-8, 10-11, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (KR 20190053025 A, given in IDS) in view of Hwang et al. (US 9245978 B2, given in IDS).
Ji teaches a thin film transistor manufacturing method comprising:
forming a data electrode (110, page 4 par 1 “source electrode”) on one side (left, FIG. 2) of a substrate (110, page 5 par 1);
forming a spacer layer (120, page 4 par 1 “insulating pattern”) on a portion of the data electrode (110) and the other side (right) of the substrate (100);
forming a drain electrode (130, page 3 par 4) on a top surface of the spacer layer (120);
forming an active layer (200, page 4 par 1 on a sidewall of the spacer layer (120), the drain electrode (130), and the data electrode (110); and
forming a gate insulation film (142, page 5 par 3) exposing the active layer (200) on the drain electrode (130) and the data electrode (110) and covering the active layer (200) on the sidewall of the spacer layer (120).
Ji does not teach forming a doped layer on the gate insulation film and the active layer outside the gate insulation film to form impurity regions at both sides, respectively, of the active layer.
Hwang teaches forming a doped layer (240, col 3 line 48 “doping source film”) on the gate insulation film (250, col 3 line 49) and the active layer (210, col 3 line 55) outside the gate insulation film (250) to form impurity regions (222 and 224, col 3 line 55) at both sides, respectively, of the active layer (210, FIG 4E).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hwang into the structure of Ji since Hwang teaches a TFT semiconductor device.
The ordinary artisan would have been motivated to modify Hwang in combination with Ji in the above manner for the motivation of integrating a doping layer to form impurity regions to create a device with high current drivability. Col 1 line 66 states, “The present disclosure has been made in an effort to provide a transistor with high current drivability and excellent uniformity, by preventing an expansion of an unnecessary doping region occurring when a self-aligned structure is formed using a doping source film.”
Re Claim 3 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 1, wherein the gate insulation film (Ji, 142) comprises a silicon oxide (Page 5 par 3 states, “A gate insulating film 142 is, for example, may include a silicon oxide (SiO .sub.2).”).
Re Claim 7 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 1, wherein the impurity regions (Hwang, 222 and 224) contain hydrogen ions or hydrogen molecules (Col 3 line 63 states, “The doping barrier 230 is formed to delay the diffusion of doping materials (hydrogen, and the like)…”)..
Re Claim 8 Ji in view of Hwang, and Jo teaches the thin film transistor manufacturing method of claim 1, wherein the spacer layer (Ji, 120) comprises a silicon oxide or a silicon nitride (Page 4 par 3 states, “The insulating pattern 120 may comprise silicon oxide (SiO .sub.x ) or silicon nitride (SiN.sub.x ).”) .
Re Claim 10 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 1, further comprising forming a gate electrode (Hwang, 260) on the doped layer (240, FIG. 4C, 250 is on a sidewall of 240, and 260 is a sidewall of 250).
Re Claim 11 Ji teaches a thin film transistor manufacturing method comprising:
forming a data electrode (110, page 4 par 1 “source electrode”) on one side (left, FIG. 2) of a substrate (110, page 5 par 1);
forming a first spacer layer (120, page 4 par 1 “insulating pattern”) on a portion of the data electrode and the other side (right) of the substrate (110);
forming a gate electrode (140, page 5 par 3) on a top surface of the first spacer layer (120);
forming a second spacer (122, page 4 last par) layer on the gate electrode (140) and the first spacer layer (120);
forming a drain electrode (130) on a top surface of the second spacer layer (122);
forming a gate insulation film (142, page 5 par 3) on a sidewall of each of the first spacer layer (120), the gate electrode (140), the second spacer layer (122), and the drain electrode (130), and the data electrode (110); and
Ji does not teach explicitly teach forming the gate insulation layer prior to forming the active layer.
Ji does teach forming an active layer (200, page 4 par 0) on the gate insulation film (142), the data electrode (110), and the drain electrode (130, FIG. 2, Ji teaches forming a gate insulation film and an active region, the order does not matter for chip functionality.).
The ordinary artisan would have been motivated to modify Ji in combination with Ji in the above manner for the motivation of applying an active layer and a gate insulation layer to form a transistor device. The abstract shows the active region and gate insulation layers are critical to chip functionality but not the order they are integrated onto the chip. The abstract page 1 par 1 states, “According to an embodiment of the present invention, a thin film transistor comprises: a substrate; a source electrode on the substrate; an insulating pattern disposed on the substrate and covering a part of an upper surface of the source electrode; a drain electrode on the insulating pattern; a spacer disposed on a side surface of the insulating pattern and on a side surface of the drain electrode; an active layer disposed on a surface of the spacer and extending from the drain electrode to the source electrode; and a gate electrode on the active layer.”
Ji does not teach forming a doped barrier layer exposing the active layer on the drain electrode and the data electrode and covering the active layer on the spacer layers; and
forming a doped layer on the doped barrier layer, the active layer outside the doped barrier layer, and the drain electrode to form impurity regions in the active layer outside the doped barrier layer.
Hwang teaches forming a doped barrier layer (230, col 3 line 48) exposing the active layer (210) on the drain electrode (284) and the data electrode (282) and covering the active layer (210) on the spacer layers (2nd patent does not teach spacer layer, it was taught in primary reference); and
forming a doped layer (240) on the doped barrier layer (230), the active layer (210) outside the doped barrier layer (230), and the drain electrode (282) to form impurity regions (222 and 224, col 3 line 55) in the active layer (210) outside the doped barrier layer (230).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hwang into the structure of Ji since Hwang teaches a TFT semiconductor device.
The ordinary artisan would have been motivated to modify Hwang in combination with Ji in the above manner for the motivation of integrating a doping and doping barrier to form impurity regions to create a device with high current drivability. Col 1 line 66 states, “The present disclosure has been made in an effort to provide a transistor with high current drivability and excellent uniformity, by preventing an expansion of an unnecessary doping region occurring when a self-aligned structure is formed using a doping source film.”
Re Claim 15 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 11, wherein the impurity regions (Hwang, 222 and 224) contain hydrogen ions or hydrogen molecules (Col 3 line 63 states, “The doping barrier 230 is formed to delay the diffusion of doping materials (hydrogen, and the like)…”)..
Claim(s) 2 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (KR 20190053025 A, given in IDS) in view of Hwang et al. (US 9245978 B2, given in IDS) and further in view of Ma et al. (CN 114551542 A).
Re Claim 2 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 1, but does not teach the gate insulation film is formed using a self-alignment method.
Ma teaches the gate insulation film is formed using a self-alignment method (page 11 par 3 states, “…using the patterning process and self-alignment process, the gate insulating material layer is formed…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ma into the structure of Ji in view of Hwang since Ma is a patent about TFT’s.
The ordinary artisan would have been motivated to modify Ma in combination with Ji in view of Hwang in the above manner for the motivation of using a self alignment method to optimize the process of forming the gate insulation film. Page 2 par 4 states, “The invention claims a display panel and a manufacturing method thereof, which can optimize the manufacturing process flow and structure between the current source/drain layer and positive electrode layer.”
Re Claim 12 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 1, but does not teach the gate insulation film is formed using a self-alignment method.
Ma teaches the gate insulation film is formed using a self-alignment method (page 11 par 3 states, “…using the patterning process and self-alignment process, the gate insulating material layer is formed…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ma into the structure of Ji in view of Hwang since Ma is a patent about TFT’s.
The ordinary artisan would have been motivated to modify Ma in combination with Ji in view of Hwang in the above manner for the motivation of using a self-alignment method to optimize the process of forming the gate insulation film. Page 2 par 4 states, “The invention claims a display panel and a manufacturing method thereof, which can optimize the manufacturing process flow and structure between the current source/drain layer and positive electrode layer.”
Re Claim 13 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 11, wherein the doped barrier layer is formed (Hwang, 230) but does not teach using a self-alignment method.
Ma teaches using a self-alignment method (page 11 par 3 states, “…using the patterning process and self-alignment process, the gate insulating material layer is formed…” The process was applied for another layer and can be repeated for other layers).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ma into the structure of Ji in view of Hwang since Ma is a patent about TFT’s.
The ordinary artisan would have been motivated to modify Ma in combination with Ji in view of Hwang in the above manner for the motivation of using a self-alignment method to optimize the process of forming the doped barrier layer. Page 2 par 4 states, “The invention claims a display panel and a manufacturing method thereof, which can optimize the manufacturing process flow and structure between the current source/drain layer and positive electrode layer.”
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (KR 20190053025 A, given in IDS) in view of Hwang et al. (US 9245978 B2, given in IDS) and further in view of Qiu et al. (US 20200075778 A1).
Re Claim 4 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 1, wherein the doped layer comprises a material containing hydrogen ions or hydrogen molecules (Col 3 line 63 states, “The doping barrier 230 is formed to delay the diffusion of doping materials (hydrogen, and the like)…”).
Ji in view of Hwang does not teach wherein the doped layer comprises a metal oxide or semiconductor oxide.
Qiu teaches the doped layer (130, FIG. 2A) comprises a metal oxide (Page 4 par 1 states, “The doped layers (130, 135)…comprise material comprising…aluminum oxide…”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Qiu into the structure of Ji in view of Hwang since Qiu is a patent about TFT’s.
The ordinary artisan would have been motivated to modify Qiu in combination with Ji in view of Hwang in the above manner for the motivation of using a metal oxide to form the doped layer to help keep the device deposition temperature low. [0003] states, “These metal oxide and metal oxynitride TFTs have the benefits of low deposition temperature…”
Re Claim 5 Ji in view of Hwang and Qiu teaches the thin film transistor manufacturing method of claim 4, but does not teach the metal oxide comprises an aluminum oxide (Qiu, Page 4 par 1 states, “The doped layers (130, 135)…comprise material comprising…aluminum oxide…”).
Re Claim 6 Ji in view of Hwang and Qiu teaches the thin film transistor manufacturing method of claim 4, wherein the semiconductor oxide comprises a silicon oxide (Qiu, Page 4 par 1 states, “The doped layers (130, 135)…comprise material comprising…silicon dioxide…”).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (KR 20190053025 A, given in IDS) in view of Hwang et al. (US 9245978 B2, given in IDS) and further in view of Jhu et al. (US 20200303481 A1).
Re Claim 9 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 1, but does not teach the active layer comprises an indium gallium zinc oxide.
Jhu teaches the active layer comprises an indium gallium zinc oxide ([0028] states, “…the active layer OS may be an indium gallium zinc oxide (IGZO) layer.”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lou into the structure of Ji in view and Hwang since Jhu is a patent about TFT’s.
The ordinary artisan would have been motivated to modify Jhu in combination with Ji in view of Hwang in the above manner for the motivation of using an active layer comprising indium gallium zinc oxide. [0002] states, “Oxide semiconductor thin film transistors have the advantages of high electron mobility, low leakage current, and simple process, and are considered as one of the mainstream thin film transistor technologies in the future.”
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (KR 20190053025 A, given in IDS) in view of Hwang et al. (US 9245978 B2, given in IDS) and further in view of Baraskar et al. (US 11322509 B2).
Re Claim 14 Ji in view of Hwang teaches the thin film transistor manufacturing method of claim 11, but does not teach the doped barrier layer comprises a silicon nitride or a metal oxide.
Baraskar teaches the doped barrier layer (970, col 85 line 3 “diffusion barrier layer”) comprises a silicon nitride.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Or-Bach into the structure of Ji in view of Hwang since Or-Bach is a patent a semiconductor structure.
The ordinary artisan would have been motivated to modify Or-Bach in combination with Ji in view of Hwang in the above manner for the motivation of using a doped barrier layer to protect the under layers during the manufacturing process. Col 84 line 56 states, “Referring to FIG. 53B, a first silicon nitride diffusion barrier layer 970 can be formed on the physically exposed surfaces of the sixth exemplary structure by a conformal deposition process.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 12/17/25