DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/06/2026 has been considered by the examiner.
Response to Amendment
Receipt is acknowledged of applicant' s amendment filed 03/06/2026. Claims 11-20 are withdrawn to an invention non-elected Claims 1-10 are pending and an action on the merits follows.
Title has been amended; previous objection withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 has been considered but are moot because the new ground of rejection in light of applicant’s amendment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210134916 A1) (Lee, hereafter) in view of Ko et al. ( US 20230200157 A1) (Ko, hereafter) in further view of Zhan et al. (US 20240194705 A1) (Zhan, hereafter).
Lee discloses, a display device comprising (Figure 1- 10 and corresponding text): (Figures 3 and 7) a substrate(110); a semiconductor (A1) on the substrate(110); a first gate insulating layer (113) on the semiconductor (A1); a gate electrode(G1) on the first gate insulating layer (113), and overlapping with the semiconductor (A1) (π73-π82); a signal line (not shown, π4 ) spaced from the gate electrode (G1); an interlayer insulating layer( 115)on the gate electrode (A1); a source electrode (S1) on the interlayer insulating layer (115), and connected to a first region of the semiconductor (A1); a drain electrode (D1) on the interlayer insulating layer (115), and connected to a second region of the semiconductor (A1); Lee fails to explicitly disclose wherein a sacrificial layer on the signal line, and comprising an amorphous silicon material; connecting member on the interlayer insulating layer, and connected to the signal line; wherein the sacrificial layer does not contact the substrate
Ko discloses (Figure 4) a sacrificial layer (103) stacked upon the driving TFT and the switching TFT and formed of amorphous silicon (π96-π97) and covering the voltage supply lines (186a,186b) (π101); (first and second connecting lines (185a/186a,185b/186b)on the interlayer (143) (π114) allowing voltage to be applied to the source and drain of the TFT to drive the display .
Zhan discloses the sacrificial layer includes(Figures 1-3,π51-π53) : a first portion and a second portion which are connected with each other, a part of the first portion close to the gate line or the signal reading line protruding from the second portion; a line width of a part of the signal reading line close to the first portion is smaller than a line width of a part of the signal reading line close to the second portion, and a line width of a part of the gate line close to the first portion is smaller than a line width of a part of the gate line close to the second portion (π47-π52); (Figure 2) sacrificial layer is formed on a side of a thin film transistor away from the base substrate
It would have been obvious for one of ordinary skill in the art before the effective filing date to modify the display device of Lee as disclosed by Ko and Zhan wherein a sacrificial layer on the signal line, and comprising an amorphous silicon material; connecting member on the interlayer insulating layer, and connected to the signal line the motivation being to suppress leakage current thus preventing bright spots and bright lines from appearing on a non-operational screen (Ko, π006) and wherein the sacrificial layer does not contact the substrate, as disclosed by Zhan, the motivation being to prevent leakage of current thus causing instability if the tft.(Zhan, π05).
Claims 2-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210134916 A1) (Lee, hereafter) in view of Ko et al. (US 20230200157 A1) (Ko, hereafter) in view of Zhan et al. (US 20240194705 A1) (Zhan, hereafter) and in further view of Kim et al. ( US 20160217743 A1) ( Kim, hereafter).
Regarding claim 2, Lee as modified by Ko and Zhan discloses the device set forth above(see rejection claim 1). Lee further discloses (Figure 4- 7): a second gate insulating layer (114) on the gate electrode (A1); and a storage electrode (Ce2) on the second gate insulating layer (114) , and overlapping with the gate electrode (G1). Lee as modified by Ko and Zhan fail to explicitly disclose wherein the signal line comprises: a first signal line at a same layer as that of the gate electrode; and a second signal line at a same layer as that of the storage electrode.
Kim discloses each of the driving transistors may include: a storage capacitor including a first storage electrode formed on the same layer as that of the first signal lines; and a second storage electrode overlapping the first storage electrode and formed on the first insulating layer, in which the first storage electrode is a driving gate electrode π18 a second signal line at a same layer as that of the storage electrode (CE2)(π18) (Examiner note first storage electrode is gate electrode); and may be formed on the same layer as that of the plurality of first signal line connecting members.
It would have been obvious for one of ordinary skill in the art before the effective filing date to further modify the device of Lee as disclosed by Kim wherein the signal line comprises: a first signal line at a same layer as that of the gate electrode; and a second signal line at a same layer as that of the storage electrode the motivation being to control capacitance as well lower manufacturing costs by utilizing the same material.
Regarding claim 3, Lee fails to disclose wherein the sacrificial layer comprises: a first sacrificial layer directly on the first signal line; and a second sacrificial layer directly on the second signal line.
Ko discloses (Figures 1-8 and corresponding text) First and second aging voltage lines (186a and 186b) are formed on the upper surface of the support substrate (101), and the sacrificial layer(103) is formed on the support substrate (101) and the first and second aging voltage lines (186a and 186b) to cover the first and second aging voltage lines (186a and 186b). Ko fails to explicitly disclose two separate layers.
It would have been obvious for one of ordinary skill in the art before the effective filing date to modify the device of Lee as disclosed by Ko wherein the sacrificial layer comprises: a first sacrificial layer directly on the first signal line; and a second sacrificial layer directly on the second signal line the motivation being to suppress leakage current thus preventing bright spots and bright lines from appearing on a non-operational screen (Ko, π006).
Regarding claims 4-7 and 9, the limitations wherein: the first sacrificial layer is further directly on the gate electrode; and the second sacrificial layer is further directly on the storage electrode (claim 4);, wherein: the first sacrificial layer has same planar shapes as those of the gate electrode and the first signal line; and the second sacrificial layer has same planar shapes as those of the storage electrode and the second signal line (claim 5); , wherein the connecting member comprises: a first connecting member connected to the first signal line; and a second connecting member connected to the second signal line, wherein the first connection member extends through the interlayer insulating layer, the second gate insulating layer, and the first sacrificial layer to be connected to the first signal line, and wherein the second connection member extends through the interlayer insulating layer and the second sacrificial layer to be connected to the second signal line (claim 6); wherein: a bottom surface of the first connecting member is in contact with the first signal line, and a side surface of the first connecting member is surrounded by the interlayer insulating layer, the second gate insulating layer, and the first sacrificial layer; and a bottom surface of the second connecting member is in contact with the second signal line, and a side surface of the second connecting member is surrounded by the interlayer insulating layer and the second sacrificial layer (claim 7); wherein the sacrificial layer is directly on the second signal line and the storage electrode (claim 9) etc do not appear to contain any additional features which define more than slight constructional changes which come within the scope of the customary (design) practice followed by persons skilled in the art, especially as the advantages thus achieved can be readily contemplated in advance. Alternatively, these limitations are not deemed patentable since the applicant’s disclosure fails to show such limitations to solve any problems or to yield any unobvious advantage that is not within the scope of the teachings applied. Therefore, such limitations would be a matter of design alternative.
One of ordinary skill in the art before the effective filing date would modify the display device of Lee based on the disclosures of both Lee and Ko, to derive the limitations set forth above for the purpose of optimization and since matters of design alternative requires only routine skill
Regarding claim 8, Lee fails to disclose wherein the first sacrificial layer and the second sacrificial layer are on an entirety of the substrate.
Ko discloses (Figures 1-8) and corresponding text where the sacrificial layer is one layer (103) and disposed entirely upon the substrate (105).
It would have been obvious for one of ordinary skill in the art before the effective filing date to modify the display device of Lee as disclosed by Ko wherein the first sacrificial layer and the second sacrificial layer are on an entirety of the substrate to promote adhesion between the support substrate and the main substrate.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210134916 A1) (Lee, hereafter) in view of Ko et al. US 20230200157 A1 (Ko, hereafter) in view of Zhan et al. (US 20240194705 A1) (Zhan, hereafter) and in further view of Kong et al. (US 20210318733 A1) (Kong, hereafter).
Lee as modified by Ko and Zhan disclose the display device set forth above (see rejection claim 1). Lee as modified by Ko fail to explicitly disclose wherein the signal line comprises: a lower signal line comprising aluminum; and an upper signal line on the lower signal line, and comprising titanium.
Kong discloses (Figure 1-8)-discloses a display device comprising: a base layer comprising: a first portion; a second portion extending from the first portion; and a third portion extending from the second portion, in a direction away from the first portion; a first light emitting element, a second light emitting element and a third light emitting element on the first portion in order along the base layer; a first upper signal line, a second upper signal line and a third upper signal line on the first portion in order along the base layer and electrically connected to the first light emitting element, the second light emitting element and the third light emitting element, respectively; a first lower signal line, a second lower signal line and a third lower signal line on the third portion in order along the base layer; and a first connection line, a second connection line and a third connection line on the second portion, electrically connecting the first upper signal line, the second upper signal line and the third upper signal line to the first lower signal line, the second lower signal line and the third lower signal line, respectively, wherein the first upper signal line and the third upper signal line on the first portion of the base layer each comprises a first metal material, and the second upper signal line on the first portion of the base layer and the first connection line, the second connection line and the third connection line on the second portion of the base layer each comprises a second metal material which is different from the first metal material. In an embodiment, the first metal material may include molybdenum (Mo). In the embodiment, the second metal material may include at least one of aluminum (Al) and titanium (Ti).
One of ordinary skill in the art before the effective filing date would modify the display device of Lee as disclosed by Kong wherein the signal line comprises: a lower signal line comprising aluminum; and an upper signal line on the lower signal line, and comprising titanium the motivation being having a narrow bezel and improved display quality (Kong, π06).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACIE Y GREEN whose telephone number is (571)270-3104. The examiner can normally be reached Mon-Thursday, 10am-8pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R Greece can be reached at (571)272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TRACIE Y. GREEN
Primary Examiner
Art Unit 2875
/TRACIE Y GREEN/Primary Examiner, Art Unit 2875