DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 13, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak (U.S. Patent Pub. No. 2010/0013816; already of record) in view of Yamashita (U.S. Patent Pub. No. 2006/0022305; already of record in IDS).
Regarding claim 1, Kwak discloses a pixel (110), (fig. 2, [0036]), comprising:
an organic light-emitting diode (OLED) connected to a first voltage line (ELVSS) configured to apply a first power voltage (ELVSS), (fig. 2, [0036]);
a first transistor (T3) configured to transmit a driving current to the OLED, wherein the first transistor has a gate electrode connected to a first node (N2) and wherein the first transistor is connected between a second node (i.e. node between T3 and T6) and a third node (N1), (fig. 2, [0042]);
a second transistor (T2) connected between a data line (Dm) and the third node (N1) and having a gate electrode connected to a corresponding scan line (Sn), (fig. 2, [0041]);
a storage capacitor (C1) connected between the first node (N2) and a second voltage line (ELVDD) configured to apply a second power voltage (ELVDD), (fig. 2, [0047]);
a first capacitor (C2) connected between the first node (N2) and the gate electrode of the second transistor (T2), (fig. 2, [0048]);
a third transistor (T4) connected between the first node (N2) and the second node and having a gate electrode connected to the corresponding scan line (Sn), (fig. 2, [0043]);
a fourth transistor (T5) connected between the second voltage line (ELVDD) and the third node (N1) and having a gate electrode connected to a light-emitting control line (En), (fig. 2, [0044]);
a fifth transistor (T6) connected between the second node and the OLED and having a gate electrode connected to the light-emitting control line (En), (fig. 2, [0045]);
a sixth transistor (T7) connected to the first node (N2) and having a gate electrode connected to a previous scan line (Sn-1), (fig. 2, [0046]); and
a seventh transistor (T1) connected between an anode electrode of the OLED and a third voltage line (Vinit) configured to apply a third power voltage (Vinit), (fig. 2, [0037]).
However, Kwak does not mention a variable third power voltage of two or more voltage levels.
In a similar field of endeavor, Yamashita teaches:
a seventh transistor (TR5) connected between an anode electrode of the OLED (42) and a third voltage line (45) configured to apply a variable third power voltage (RAMP 60) of two or more voltage levels (i.e. ramp voltage line 45 applies a ramp voltage RAMP to transistor TR5 through capacitor C2 which has multiple voltage levels decreasing monotonically) determined based on a characteristic of a panel (i.e. based on the light emission period of the display panel 4), such that the two or more voltage levels (i.e. ramp voltage RAMP has multiple decreasing voltage levels) are configured to be applied to the seventh transistor (TR5) during an entire duration of respective light-emitting periods (i.e. RAMP voltage is applied during light emission periods of a first frame and frames following the first frame), (figs. 2-3, [0160, 0169-0170 and 0175]),
wherein the third power voltage (RAMP 60) is less than the first power voltage (CV) (i.e. voltage RAMP decreases below voltage CV during light emission period), (fig. 3, [0169 and 0175]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak, by specifically providing the variable third power voltage, as taught by Yamashita, for the purpose of reducing variation of brightness attributable to time-related or temperature-related variation with no increase in power consumption, [0024].
Regarding claim 2, Kwak discloses wherein the sixth transistor (T7) is connected to the third voltage line (Vinit), (fig. 2, [0046]).
Regarding claim 3, Yamashita discloses wherein the third power voltage (RAMP) is configured to be supplied by a variable voltage supply source configured to supply a DC voltage (i.e. direct-current component of the ramp voltage), (fig. 3, [0606]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak, by specifically providing the variable voltage, as taught by Yamashita, for the purpose of reducing variation of brightness attributable to time-related or temperature-related variation with no increase in power consumption, [0024].
Regarding claim 4, Yamashita discloses wherein the third voltage line (45) is connected to a variable power source (RAMP) and wherein the variable power source is configured to be controlled when the OLED (42) emits light (i.e. the voltage RAMP is controlled to decrease monotonically during the light emission period), (figs. 2-3, [0175]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak, by specifically providing the variable power source, as taught by Yamashita, for the purpose of reducing variation of brightness attributable to time-related or temperature-related variation with no increase in power consumption, [0024].
Regarding claim 7, Kwak discloses wherein:
a gate electrode of the seventh transistor (T1) is connected to the corresponding scan line (Sn-1), and
wherein the third power voltage (Vinit) is configured to be applied to the anode electrode of the OLED while a scan signal (Sn-1) transmitted from the corresponding scan line (Sn-1) is transmitted with a voltage level (i.e. low voltage) for turning on the seventh transistor (T1), (figs. 2-3, [0036-0037]).
Regarding claim 8, Kwak discloses wherein a gate electrode of the seventh transistor (T1) is connected to the previous scan line (Sn-1), and
wherein the third power voltage (Vinit) is configured to be applied to the anode electrode of the OLED while a scan signal transmitted from the previous scan line (Sn-1) is transmitted with a voltage level (i.e. low voltage level) for turning on the seventh transistor (T1), (figs. 2-3, [0038-0039]).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak in view of Yamashita and in view of Osame et al (U.S. Patent Pub. No. 2005/0259093; already of record in IDS).
Regarding claim 5, Kwak in view of Yamashita discloses everything as specified above in claim 1. However, Kwak in view of Yamashita does not mention wherein a gate electrode and a source electrode of the seventh transistor are both connected to a node formed between the first transistor and the OLED.
In a similar field of endeavor, Osame teaches wherein a gate electrode and a source electrode of the seventh transistor (gate and source of P-channel transistor of fig. 2c) are both connected to a node (P1) formed between the first transistor (14) and the OLED (15), (figs. 1 and 2c, [0041-0042 and 0050-0051]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak in view of Yamashita, by specifically providing the gate electrode and a source electrode of the seventh transistor are both connected to a node formed between the first transistor and the OLED, as taught by Osame, for the purpose of having a pass element to allow the off current o flow outside, [0009].
Regarding claim 6, Osame discloses wherein a gate electrode of the seventh transistor (20) is connected to a DC voltage supply source (12), (fig. 6a, [0089]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak in view of Yamashita, by specifically providing the gate of the seventh transistor connected to a DC voltage supply source, as taught by Osame, for the purpose of having a pass element to allow the off current o flow outside, [0009].
Claim(s) 9-12 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak in view of Yamashita and in view of Choi et al (U.S. Patent Pub. No. 2011/0084958; already of record).
Regarding claim 9, Kwak discloses an organic light-emitting diode (OLED) display (fig. 1, [0028]), comprising:
a scan driver (200) configured to transmit a plurality of scan signals to a plurality of scan lines (S0-Sn), (fig. 1, [0033]);
a data driver (300) configured to transmit a plurality of data signals to a plurality of data lines (D1-Dm), (fig. 1, [0034]);
an emission control driver (200) configured to transmit a plurality of light emission control signals to a plurality of emission control lines (E1-En), (fig. 1, [0033]);
a display unit (100) comprising a plurality of pixels (110) that are connected to corresponding scan lines (S0-Sn), corresponding data lines (D1-Dm) and corresponding emission control lines (E1-En), wherein the display unit is configured to display an image by emitting light according to the data signals and the light emission control signals, (fig. 1, [0029-0031]);
a power supply configured to respectively supply a first power voltage (ELVSS), a second power voltage (ELVDD), and a third power voltage (Vinit) to the pixels (110) via first, second, and third voltage lines (ELVSS, ELVDD and Vinit, respectively), (figs. 1-2, [0032 and 0037]); and
wherein the pixels (110) respectively comprise:
an organic light-emitting diode (OLED) connected to the first voltage line (ELVSS) configured to apply the first power voltage (ELVSS), (fig. 2, [0036]);
a first transistor (T3) configured to transmit a driving current to the OLED, wherein the first transistor has a gate electrode connected to a first node (N2) and wherein the first transistor is connected between a second node (i.e. node between T3 and T6) and a third node (N1), (fig. 2, [0042]);
a second transistor (T2) connected between a data line (Dm) and the third node (N1) and having a gate electrode connected to a corresponding scan line (Sn), (fig. 2, [0041]);
a storage capacitor (C1) connected between the first node (N2) and the second voltage line (ELVDD) configured to apply the second power voltage (ELVDD), (fig. 2, [0047]);
a first capacitor (C2) connected between the first node (N2) and the gate electrode of the second transistor (T2), (fig. 2, [0048]);
a third transistor (T4) connected between the first node (N2) and the second node and having a gate electrode connected to the corresponding scan line (Sn), (fig. 2, [0043]);
a fourth transistor (T5) connected between the second voltage line (ELVDD) and the third node (N1) and having a gate electrode connected to a light-emitting control line (En), (fig. 2, [0044]);
a fifth transistor (T6) connected between the second node and the OLED and having a gate electrode connected to the light-emitting control line (En), (fig. 2, [0045]);
a sixth transistor (T7) connected to the first node (N2) and having a gate electrode connected to a previous scan line (Sn-1), (fig. 2, [0046]); and
the seventh transistor (T1) connected between an anode electrode of the OLED and the third voltage line (Vinit), (fig. 2, [0037]).
However, Kwak does not mention the third power voltage being a variable power voltage of two or more voltage levels determined based on a characteristic of a panel.
In a similar field of endeavor, Yamashita teaches:
a power supply (8) configured to supply a third power voltage (RAMP) to the pixels via the third voltage lines (45), the third power voltage being a variable power voltage of two or more voltage levels (i.e. ramp voltage line 45 applies a ramp voltage RAMP to transistor TR5 through capacitor C2 which has multiple voltage levels decreasing monotonically) determined based on a characteristic of a panel (i.e. based on the light emission period of the display panel 4) such that the two or more voltage levels are configured to be applied to a seventh transistor (TR5) during an entire duration of respective light-emitting periods (i.e. RAMP voltage is applied during light emission periods of a first frame and frames following the first frame), (figs. 1-3, [0160, 0169-0170 and 0175]),
wherein the third power voltage (RAMP 60) is less than the first power voltage (CV), (i.e. voltage RAMP decreases below voltage CV during light emission period), (fig. 3, [0169 and 0175]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak, by specifically providing the variable third power voltage, as taught by Yamashita, for the purpose of reducing variation of brightness attributable to time-related or temperature-related variation with no increase in power consumption, [0024].
However, Kwak in view of Yamashita does not mention the controller configured to control the power supply.
In a similar field of endeavor, Choi teaches:
a controller (150) configured to i) control the scan driver (110), the data driver (120), the emission control driver (110), and the power supply (160), ii) generate the data signals, iii) supply the generated data signals to the data driver (120), iv) generate a control signal for controlling the emission control driver (110), and v) transmit the generated control signal to the emission control driver, (figs. 1 and 5, [0027-0033 and 0060]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak in view of Yamashita, by specifically providing the controller for controlling the power supply, as taught by Choi, for the purpose of controlling different modes of the display, [0009].
Regarding claim 10, Kwak discloses wherein the sixth transistor (T7) is connected to the third voltage line (Vinit), (fig. 2, [0046]).
Regarding claim 11, Choi discloses wherein the controller (150) is configured to control the power supply (160) to generate the third power voltage (Vint) as a DC voltage, (figs. 1 and 5, [0027 and 0059]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak in view of Yamashita, by specifically providing the controller for controlling the power supply, as taught by Choi, for the purpose of controlling different modes of the display, [0009].
Regarding claim 12, Yamashita discloses wherein the controller (7) is configured to control the power supply (8) to change the third power voltage (i.e. change in RAMP voltage) when the OLED emits light (i.e. during the light emission period), (fig. 3, [0163 and 0175]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak in view of Yamashita, by specifically providing the controller for controlling the power supply, as taught by Yamashita, for the purpose of reducing variation of brightness attributable to time-related or temperature-related variation with no increase in power consumption, [0024].
Regarding claim 15, Kwak discloses wherein a gate electrode of the seventh transistor (T1) is connected to the corresponding scan line (Sn-1), and
wherein the third power voltage (Vinit) is configured to be applied to the anode electrode of the OLED while a scan signal (Sn-1) transmitted from the corresponding scan line (Sn-1) is transmitted with a voltage level (i.e. low voltage) for turning on the seventh transistor (T1), (fig. 2, [0037-0038]).
Regarding claim 16, Kwak discloses wherein:
a gate electrode of the seventh transistor (T1) is connected to the previous scan line (Sn-1), and
wherein the third power voltage (Vinit) is configured to be applied to the anode electrode of the OLED while a scan signal transmitted from the previous scan line (Sn-1) is transmitted with a voltage level (i.e. low voltage level) for turning on the seventh transistor (T1), (figs. 2-3, [0037-0039]).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak in view of Yamashita in view of Choi and in view of Osame.
Regarding claim 13, Kwak in view of Yamashita and in view of Choi discloses everything as specified above in claim 9. However, Kwak in view of Yamashita and in view of Choi does not mention wherein a gate electrode and a source electrode of the seventh transistor are both connected to a node formed between the first transistor and the OLED.
In a similar field of endeavor, Osame teaches wherein a gate electrode and a source electrode of the seventh transistor (i.e. gate and source of P-channel transistor of fig. 2c) are both connected to a node (P1) formed between the first transistor (14) and the OLED (15), (figs. 1 and 2c, [0041-0042 and 0050-0051]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak in view of Yamashita and in view of Choi, by specifically providing the gate electrode and a source electrode of the seventh transistor are both connected to a node formed between the first transistor and the OLED, as taught by Osame, for the purpose of having a pass element to allow the off current to flow outside, [0009].
Regarding claim 14, Osame discloses wherein a gate electrode of the seventh transistor (20) is connected to a DC voltage supply source (12), (fig. 6a, [0089]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kwak in view of Yamashita and in view of Choi, by specifically providing the gate of the seventh transistor connected to a DC voltage supply source, as taught by Osame, for the purpose of having a pass element to allow the off current to flow outside, [0009].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of amendment, the reference of Yamashita has been added for new grounds of rejection.
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/LONG D PHAM/Primary Examiner, Art Unit 2623