DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 2-5, 10, 13, 17-20, 24-25, 28-31, 34-36, 38, and 41-55 are cancelled. Claims 1, 6-9, 11-12, 14-16, 21-23, 26-27, 32-33, 37, and 39-40 are present for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 03, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 23, 2023, February 28, 2024, March 11, 2025, and March 26, 2026 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: INTEGRATED CIRCUIT HAVING AN IMPROVED DEGREE OF INTEGRATION.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-9, 11-12, 14-16, 21-22, 32-33, 37, and 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0084928 A1) in view of Tanaka (US 2018/0374794 A1)
Claim 1, Chen discloses an integrated circuit (semiconductor structure is an integrated circuit, hereinafter, integrated circuit, [0018], Fig. 1) comprising:
a substrate (interposer substrate 100 is a substrate, hereinafter, substrate 100, [0023], Fig. 1) including an active region (substrate 100 includes device region 110 which is an active region, hereinafter, active region 110, [0023], Fig. 1);
an inductive element (electronic device 112 may include an inductor, hereinafter, inductive element 112, [0018], Fig. 1) adjacent to the active region 110 (inductive element 112 is adjacent to the active region 110, [0018], Fig. 1); and
first and second guard rings (guard ring 130 is a first guard ring, hereinafter, first guard ring 130 and assistant guard ring 132 is a second guard ring, hereinafter, second guard ring 132, [0018] and [0038], Figs. 1 and 11) configured to shield the active region 110 from magnetic flux generated from the inductive element 112 (first guard ring 130 and second guard ring 132 are configured to shield the active region 110 from magnetic flux generated from the inductive element 112, [0022] and [0038], Figs. 1 and 11),
wherein the inductive element 112 comprises:
a first through electrode (through-silicon via 120 in the (-X) direction is the first through electrode, hereinafter, first through electrode 120L, [0019], Figs. 1 and 11) extending in a first direction (i.e. Z direction) that is perpendicular to an upper surface of the substrate 100 (first through electrode 120L extends in the Z direction that is perpendicular to an upper surface of the substrate 100 (i.e. XY plane), [0019], Figs. 1 and 11);
an upper metallization pattern (conductive layer 142 is an upper metallization pattern, hereinafter, upper metallization pattern 142, [0020], Figs. 1 and 11) connected to the first through electrode 120L (upper metallization pattern 142 is connected to the first through electrode 120L, [0021], Figs. 1 and 11) and extending in a second direction (i.e. X direction) that is perpendicular to the first direction (i.e. Z direction) (upper metallization pattern 142 extends in the X direction, wherein the X direction is perpendicular to the Z direction), [0021], Figs. 1 and 11); and
a lower metallization pattern (conductive layer 152 is a lower metallization pattern, hereinafter, lower metallization pattern 152, [0020], Figs. 1 and 11) connected to the first through electrode 120L (lower metallization pattern 152 is connected to the first through electrode 120L, [0021], Figs. 1 and 11) and extending in the second direction (i.e. X direction) (lower metallization pattern 152 extends in the X direction, [0021], Figs. 1 and 11),
wherein the upper metallization pattern 142 and the lower metallization pattern 152 are spaced apart from each other with the first through electrode 120L therebetween (upper metallization pattern 142 and the lower metallization pattern 152 are spaced apart from each other with the first through electrode 120L therebetween, [0021], Figs. 1 and 11).
Chen does not explicitly disclose a substrate including an active region on which a plurality of transistors constituting a logic circuit are provided; and an inductive element adjacent to the active region and extending along an edge of the active region.
However, Tanaka discloses a substrate (Tanaka, substrate 2, [0019], Figs. 1 and 2; Chen, substrate 100, [0023], Fig. 1) including an active region (Tanaka, internal circuit region 4 is an active region included within the substrate 2, hereinafter, active region 4, [0020], Figs. 1 and 2; Chen, substrate 100 includes active region 110, [0023], Fig. 1) on which a plurality of transistors constituting a logic circuit are provided (Tanaka, substrate 2 includes an active region 4 which includes a transistors 10 within each cross-section and constitutes a logic circuit, [0020], Figs. 1 and 2; Chen, substrate 100 includes active region 110, [0023], Fig. 1); and an inductive element (Tanaka, inductor 5 is an inductive element, hereinafter, inductive element 5, [0019], Figs. 1 and 2; Chen, inductive element 112, [0018], Fig. 1) adjacent to the active region (Tanaka, inductive element 5 is adjacent to the active region 4, [0019], Figs. 1 and 2; Chen, inductive element 112 is adjacent to the active region 110, [0018], Fig. 1) and extending along an edge of the active region (Tanaka, inductive element 5 extends along an edge of the active region 4, [0019], Figs. 1 and 2; Chen, inductive element 112 extends along an edge of the active region 110, [0018], Fig. 1). The combination to utilize an active region adjacent to the inductive element allows for the creation of a semiconductor device with a deterioration/variation characteristic of the magnetic sensor to be minimized (Tanaka, [0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an active region adjacent to the inductive element to allow for the creation of a semiconductor device with a deterioration/variation characteristic of the magnetic sensor to be minimized (Tanaka, [0027]).
Claim 6, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 1.
Chen/Tanaka discloses wherein the inductive element (Tanaka, inductive element 5, [0019], Figs. 1 and 2; Chen, inductive element 112, [0018], Fig. 1) further comprises a second through electrode (Chen, inductive element 112 further comprises a through-silicon via 120 in the (+X) direction is the second through electrode, hereinafter, second through electrode 120R, [0018], Figs. 1 and 2; Tanaka, inductive element 5 further comprises a first through electrode 13, [0019], Figs. 1 and 11) connected to the lower metallization pattern (Tanaka, inductive element 5 further comprises a second through electrode 120R connected to the lower metallization pattern 152, [0019], Figs. 1 and 11, [0019], Figs. 1 and 2; Chen, inductive element 112 further comprises a first through electrode 13, [0018], Fig. 1) and spaced apart from the first through electrode (Tanaka, inductive element 5 further comprises a second through electrode 120R spaced apart from the first through electrode 120L, [0019], Figs. 1 and 11, [0019], Figs. 1 and 2; Chen, inductive element 112 further comprises a first through electrode 13, [0018], Fig. 1).
Claim 7, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 6.
Chen/Tanaka discloses wherein a portion of the substrate (Tanaka, substrate 2, [0019], Figs. 1 and 2; Chen, substrate 100, [0023], Fig. 1) is between the first through electrode and the second through electrode (Tanaka, a portion of the substrate 2 and first through electrode 13, [0019], Figs. 1 and 2; Chen, a portion of the substrate 100 is between the first through electrode 120L and the second through electrode 120R, [0023], Fig. 1).
Claim 8, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 6.
Chen/Tanaka discloses further comprising a first permeability control layer (Tanaka, first permeability control layer 11, [0020], Figs. 1 and 2; Chen, dielectric layer 141 of the first redistribution layer 140 is a first permeability control layer, hereinafter, first permeability control layer 141, [0023], Fig. 1) between the first through electrode and the second through electrode (Tanaka, first permeability control layer 11 and first through electrode 13, [0019], Figs. 1 and 2; Chen, first permeability control layer 141 is between the first through electrode 120L and the second through electrode 120R, [0023], Fig. 1) and having a permeability that is different from that of the substrate (Tanaka, first permeability control layer 11 has a permeability that is different from that of the substrate 2, [0019], Figs. 1 and 2; Chen, first permeability control layer 141 has a permeability that is different from that of the substrate 100 (i.e. (bulk) silicon substrate vs. SiO2, SiN, polyimide (PI), etc., [0023], Fig. 1).
Claim 9, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 8.
Chen/Tanaka discloses wherein the first permeability control layer is between the substrate and the upper metallization pattern (Tanaka, first permeability control layer 11 is between the substrate 2 and the upper metallization pattern 12, [0019], Figs. 1 and 2; Chen, first permeability control layer 141 is between the substrate 100 and the upper metallization pattern 142, [0023], Fig. 1).
Claim 11, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 8.
Chen/Tanaka discloses further comprising a second permeability control layer (Tanaka, multilayer wiring layer 3 is a second permeability control layer, hereinafter, second permeability control layer 3, [0020], Figs. 1 and 2; Chen, dielectric layer 151 of the second redistribution layer 150 is a second permeability control layer, hereinafter, second permeability control layer 151, [0023], Fig. 1) on the first permeability control layer (Tanaka, second permeability control layer 3 is on the first permeability control layer 11, [0020], Figs. 1 and 2; Chen, second permeability control layer 151 is on the first permeability control layer 141, [0023], Fig. 1) and between the first and second through electrodes (Tanaka, second permeability control layer 3 is on the first permeability control layer 11 and first through electrode 13, [0019], Figs. 1 and 2; Chen, second permeability control layer 151 is on the first permeability control layer 141 and is between the first through electrode 120L and the second through electrode 120R, [0023], Fig. 1) and having a permeability different from that of the substrate (Tanaka, second permeability control layer 3 has a permeability that is different from that of the substrate 2, [0019], Figs. 1 and 2; Chen, second permeability control layer 151 has a permeability that is different from that of the substrate 100 (i.e. (bulk) silicon substrate vs. SiO2, SiN, polyimide (PI), etc., [0023], Fig. 1).
Claim 12, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 1.
Chen/Tanaka discloses wherein a gate electrode of the transistor (Tanaka, gate electrode of the transistor 10, hereinafter, gate electrode of the transistor 10G, [0020], Figs. 1 and 2; Chen, substrate 100 includes active region 110, [0023], Fig. 1) extends in the second direction (Tanaka, gate electrode of the transistor 10G extends in the second direction (i.e. X direction), [0020], Figs. 1 and 2; Chen, substrate 100 includes active region 110, [0023], Fig. 1).
Claim 14, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 1.
Chen/Tanaka discloses wherein the upper metallization pattern, the lower metallization pattern, and the first through electrode of the inductive element constitute a wound structure (Tanaka, upper metallization pattern 12, the lower metallization pattern, and the first through electrode 13 of the inductive element 5 constitute a wound structure, hereinafter, wound structure 5/12/13, [0020], Figs. 1 and 2; Chen, upper metallization pattern 142, the lower metallization pattern 152, and the first through electrode 120L of the inductive element 112 constitute a wound structure, hereinafter, wound structure 142/152/120L, [0021], Figs. 1 and 11), and
a winding axis of the inductive element (Tanaka, inductive element 5, [0019], Figs. 1 and 2; Chen, inductive element 112, [0018], Fig. 1) is parallel to a third direction that is perpendicular to each of the first and second directions (Tanaka, inductive element 5, [0019], Figs. 1 and 2; Chen, a winding axis of the inductive element 112 is parallel to a third direction (i.e. Y direction) that is perpendicular to each of the first direction (i.e. Z direction) and second direction (i.e. X direction), [0018], Fig. 1).
Claim 15, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 14.
Chen/Tanaka discloses wherein each of the first and second guard rings (Tanaka, shielding members 6/7/8/9 are a first guard ring, hereinafter, first guard ring 6/7/8/9, [0019], Figs. 1 and 2; Chen, first guard ring 130 and second guard ring 132, [0018] and [0038], Figs. 1 and 11) extends in the third direction (Tanaka, shielding members 6/7/8/9 are a first guard ring, hereinafter, first guard ring 6/7/8/9 extends in the third direction (i.e. Y direction), [0019], Figs. 1 and 2; Chen, first guard ring 130 and second guard ring 132 extends in the third direction (i.e. Y direction), [0018] and [0038], Figs. 1 and 11).
Claim 16, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 15.
Chen/Tanaka discloses wherein each of the first and second guard rings (Tanaka, first guard ring 6/7/8/9, [0019], Figs. 1 and 2; Chen, first guard ring 130 and second guard ring 132, [0018] and [0038], Figs. 1 and 11) includes a guard ring through-electrode in the substrate and extending in the third direction (Tanaka, first guard ring 6/7/8/9 includes a guard ring through-electrode in the substrate and extends in the third direction (i.e. Y direction), [0019], Figs. 1 and 2; Chen, first guard ring 130 and second guard ring 132 functions as a guard ring through-electrode in the substrate 100 and extends in the third direction (i.e. Y direction) when combined with first shielding layer 143 and second shielding layer 153, [0018] and [0038], Figs. 1, 10, and 11).
Claim 21, Chen discloses an integrated circuit (semiconductor structure is an integrated circuit, hereinafter, integrated circuit, [0018], Fig. 1) comprising:
a first guard ring (guard ring 130 is a first guard ring, hereinafter, first guard ring 130, [0018] and [0038], Figs. 1 and 11);
a second guard ring (assistant guard ring 132 is a second guard ring, hereinafter, second guard ring 132, [0018] and [0038], Figs. 1 and 11) spaced apart from the first guard ring 130 (second guard ring 132 is spaced apart from the first guard ring 130, [0018] and [0038], Figs. 1 and 11); and
an inductive element (electronic device 112 may include an inductor, hereinafter, inductive element 112, [0018], Fig. 1) between the first guard ring 130 and the second guard ring 132 (inductive element 112 is between the first guard ring 130 and the second guard ring 132, [0018], Fig. 1),
wherein the inductive element 112 comprises:
a first through electrode (through-silicon via 120 in the (-X) direction is the first through electrode, hereinafter, first through electrode 120L, [0019], Figs. 1 and 11) in a substrate (first through electrode 120L is within the interposer substrate 100 which is a substrate, hereinafter, substrate 100, [0023], Fig. 1);
a first upper metallization pattern (conductive layer 142 in contact with the first through electrode 120L is a first upper metallization pattern, hereinafter, first upper metallization pattern 142L, [0020], Figs. 1 and 11) connected to the first through electrode 120L (first upper metallization pattern 142L is connected to the first through electrode 120L, [0020], Figs. 1 and 11) and on an upper surface of the substrate (first upper metallization pattern 142L is on an upper surface of the substrate 100, [0020], Figs. 1 and 11);
a first lower metallization pattern (conductive layer 152 in contact with the first through electrode 120L is a first lower metallization pattern, hereinafter, first lower metallization pattern 152L, [0020], Figs. 1 and 11) connected to the first through electrode 120L (first lower metallization pattern 152L is connected to the first through electrode 120L, [0020], Figs. 1 and 11) and on a lower surface of the substrate 100 opposite to the upper surface of the substrate 100 (first lower metallization pattern 152L is on a lower surface of the substrate 100 opposite to the upper surface of the substrate 100, [0020], Figs. 1 and 11); and
a second through electrode (through-silicon via 120 in the (+X) direction is the second through electrode, hereinafter, second through electrode 120R, [0018], Figs. 1 and 2) connected to the first lower metallization pattern 152L (second through electrode 120R is connected to the first lower metallization pattern 152L, [0018], Figs. 1 and 2), in the substrate 100 (second through electrode 120R is in the substrate 100, [0018], Figs. 1 and 2), and spaced apart from the first through electrode 120L (second through electrode 120R is spaced apart from the first through electrode 120L, [0018], Figs. 1 and 2).
Chen does not explicitly disclose wherein the first upper metallization pattern, the first through electrode, the first lower metallization pattern, and the second through electrode constitute a wound structure having a winding axis extending in a first direction that is parallel to the upper surface of the substrate.
However, Tanaka discloses wherein the first upper metallization pattern, the first through electrode, the first lower metallization pattern, and the second through electrode constitute a wound structure (Tanaka, first upper metallization pattern 12, the first lower metallization pattern, and the first through electrode 13 of the inductive element 5 constitute a wound structure, hereinafter, wound structure 5/12/13, [0020], Figs. 1 and 2; Chen, first upper metallization pattern 142L, the first through electrode 120L, the first lower metallization pattern 152L, and the second through electrode 120R constitute a wound structure, hereinafter, wound structure 142L/152L/120L, [0021], Figs. 1 and 11) having a winding axis extending in a first direction that is parallel to the upper surface of the substrate (Tanaka, inductive element 5, [0019], Figs. 1 and 2; Chen, wound structure 142L/152L/120L has a winding axis parallel to a third direction (i.e. Y direction) that is perpendicular to each of the first direction (i.e. Z direction) and second direction (i.e. X direction), [0018], Fig. 1). The combination of utilizing a wound structure in combination with the semiconductor device allows for the creation of a semiconductor device with a deterioration/variation characteristic of the magnetic sensor to be minimized (Tanaka, [0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a wound structure in combination with the semiconductor device to allow for the creation of a semiconductor device with a deterioration/variation characteristic of the magnetic sensor to be minimized (Tanaka, [0027]).
Claim 22, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 21.
Chen/Tanaka discloses wherein the inductive element includes a structure wound multiple times on a cross-section perpendicular to the first direction (Chen, inductive element 112 includes a structure wound multiple times on a cross-section perpendicular to the Z direction, [0019], Figs. 1, 10, and 11; Tanaka, inductive element 5 includes a structure wound multiple times on a cross-section perpendicular to the Z direction, [0019], Figs. 1 and 2).
Claim 32, Chen discloses an integrated circuit (semiconductor structure is an integrated circuit, hereinafter, integrated circuit, [0018], Fig. 1) comprising:
an inductive element (electronic device 112 may include an inductor, hereinafter, inductive element 112, [0018], Fig. 1) extending along an edge of an active region (substrate 100 includes device region 110 which is an active region, hereinafter, active region 110 wherein the inductive element 112 extends along an edge (of an active region 110), [0023], Fig. 1);
a first guard ring (guard ring 130 is a first guard ring, hereinafter, first guard ring 130, [0018] and [0038], Figs. 1 and 11) between the active region 110 and the inductive element 112 (first guard ring 130 is between the active region 110 and the inductive element 112, [0018] and [0038], Figs. 1 and 11); and
a second guard ring (assistant guard ring 132 is a second guard ring, hereinafter, second guard ring 132, [0018] and [0038], Figs. 1 and 11) spaced apart from the first guard ring 130 (second guard ring 132 is spaced apart from the first guard ring 130, [0018] and [0038], Figs. 1 and 11) with the inductive element 112 therebetween (inductive element 112 is between the first guard ring 130 and the second guard ring 132, [0018], Fig. 1),
wherein a winding axis of the inductive element 112 extends in a first direction that is parallel to an upper surface of a substrate 100 (inductive element 112 has a winding axis extends in the X and Y directions that is parallel to an upper surface of a substrate 100, [0018], Fig. 1), and
the inductive element 112 includes a plurality of through electrodes (a plurality of through-silicon vias 120 form the first through electrode 120L in the (-X) direction and the second through electrode 120R in the (+X) direction, hereinafter, plurality of through electrodes 120, [0018], Figs. 1 and 2) that extend in a second direction (i.e. X direction) perpendicular to the upper surface of the substrate 100 (plurality of through electrodes 120 extend in the X direction and Z direction, [0018], Figs. 1 and 2) perpendicular to the upper surface of the substrate 100 (plurality of through electrodes 120 are perpendicular to the upper surface of the substrate 100, [0018], Figs. 1 and 2) and are in the substrate 100 (plurality of through electrodes 120 are in the substrate 100, [0018], Figs. 1 and 2).
Chen does not explicitly disclose an inductive element extending along an edge of an active region including a plurality of transistors.
However, Tanaka discloses an inductive element extending along an edge of an active region including a plurality of transistors.
an inductive element (Tanaka, inductor 5 is an inductive element, hereinafter, inductive element 5, [0019], Figs. 1 and 2; Chen, inductive element 112, [0018], Fig. 1) adjacent to the active region (Tanaka, inductive element 5 is adjacent to the active region 4, [0019], Figs. 1 and 2; Chen, inductive element 112 is adjacent to the active region 110, [0018], Fig. 1) and extending along an edge of the active region (Tanaka, inductive element 5 extends along an edge of the active region 4, [0019], Figs. 1 and 2; Chen, inductive element 112 extends along an edge of the active region 110, [0018], Fig. 1) including a plurality of transistors (Tanaka, substrate 2 includes an active region 4 which includes a transistors 10 within each cross-section and constitutes a logic circuit, [0020], Figs. 1 and 2; Chen, substrate 100 includes active region 110, [0023], Fig. 1). The combination to utilize an inductive element adjacent to an edge of the active region allows for the creation of a semiconductor device with a deterioration/variation characteristic of the magnetic sensor to be minimized (Tanaka, [0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an active region adjacent to the inductive element to allow for the creation of a semiconductor device with a deterioration/variation characteristic of the magnetic sensor to be minimized (Tanaka, [0027]).
Claim 33, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 32.
Chen/Tanaka discloses wherein the inductive element (Tanaka, inductive element 5, [0019], Figs. 1 and 2; Chen, inductive element 112, [0018], Fig. 1) includes a plurality of unit inductors arranged in the second direction (Tanaka, inductive element 5 includes first inductor 5a and second inductor 5b which are a plurality of unit inductors, hereinafter, plurality of unit inductors 5a/5b arranged in the X direction, [0019], Figs. 1 and 2; Chen, inductive element 112 includes a plurality of unit inductors 110 arranged in the X direction, [0026], Fig. 2).
Claim 37, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 33.
Chen/Tanaka discloses wherein each of the plurality of unit inductors includes a structure wound multiple times on a cross-section perpendicular to the first direction (Tanaka, each of the plurality of unit inductors 5a/5b includes a structure wound multiple times on a cross-section perpendicular to the Z direction, [0019], Figs. 1 and 2; Chen, each of the plurality of unit inductors 110 includes a structure wound multiple times on a cross-section perpendicular to the Z direction, [0021], Fig. 2).
Claim 39, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 33.
Chen/Tanaka discloses wherein each of the plurality of unit inductors (Tanaka, each of the plurality of unit inductors 5a/5b, [0019], Figs. 1 and 2; Chen, inductive element 112 includes a plurality of unit inductors arranged in the X direction, [0021], Fig. 1) comprises:
upper metallization patterns (Tanaka, upper metallization pattern 12, [0020], Figs. 1 and 2; Chen, upper metallization patterns 142, [0021], Figs. 1 and 11) on the upper surface of the substrate (Tanaka, upper metallization pattern 12 on the upper surface of the substrate 2, [0020], Figs. 1 and 2; Chen, upper metallization patterns 142 on the upper surface of the substrate 100, [0021], Figs. 1 and 11) and connected to at least one of the plurality of through electrodes (Tanaka, upper metallization pattern 12 connected to at least one of the plurality of through electrodes 13, [0020], Figs. 1 and 2; Chen, upper metallization patterns 142 connected to at least one of the plurality of through electrodes 120, [0021], Figs. 1 and 11); and
lower metallization patterns (Tanaka, lower metallization patterns, [0020], Figs. 1 and 2; Chen, lower metallization patterns 152, [0021], Figs. 1 and 11) on a lower surface of the substrate opposite to the upper surface thereof (Tanaka, lower metallization patterns on a lower surface of the substrate 2 opposite to the upper surface thereof, [0020], Figs. 1 and 2; Chen, lower metallization patterns 152 on a lower surface of the substrate 100 opposite to the upper surface thereof, [0021], Figs. 1 and 11) and connected to at least one of the plurality of through electrodes (Tanaka, lower metallization patterns connected to at least one of the plurality of through electrodes 13, [0020], Figs. 1 and 2; Chen, lower metallization patterns 152 connected to at least one of the plurality of through electrodes 120, [0021], Figs. 1 and 11),
wherein the upper metallization patterns and the lower metallization patterns are spaced apart from each other with the plurality of through electrodes therebetween (Tanaka, upper metallization pattern 12 and lower metallization patterns are spaced apart from each other with the plurality of through electrodes 13 therebetween, [0020], Figs. 1 and 2; Chen, upper metallization patterns 142 and lower metallization patterns 152 are spaced apart from each other with the plurality of through electrodes 120 therebetween, [0021], Figs. 1 and 11).
Claim 40, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 39.
Chen/Tanaka discloses wherein the upper metallization patterns and the lower metallization patterns extend in a third direction that is perpendicular to the first and second directions (Tanaka, upper metallization pattern 12 and lower metallization patterns extend in a third direction (i.e. Y direction) that is perpendicular to the first direction (i.e. Z direction) and second direction (i.e. X direction), [0020], Figs. 1 and 2; Chen, upper metallization patterns 142 and lower metallization patterns 152 extend in a third direction (i.e. Y direction) that is perpendicular to the first direction (i.e. Z direction) and second direction (i.e. X direction), [0021], Figs. 1 and 11).
Claims 23, 26, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Tanaka, and further in view of Huang (US 2019/0122931 A1)
Claim 23, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 21.
Chen/Tanaka discloses wherein the inductive element further comprises:
a second upper metallization pattern (Tanaka, first upper metallization pattern 12 and the first through electrode 13 of the inductive element 5, [0020], Figs. 1 and 2; Chen, conductive layer 142 in contact with the second through electrode 120R is a second upper metallization pattern, hereinafter, second upper metallization pattern 142R, [0020], Figs. 1 and 11, [0021], Figs. 1 and 11) connected to the second through electrode (Tanaka, first upper metallization pattern 12 and the first through electrode 13 of the inductive element 5, [0020], Figs. 1 and 2; Chen, second upper metallization pattern 142R is connected to the second through electrode 120R, [0020], Figs. 1 and 11, [0021], Figs. 1 and 11) and on the upper surface of the substrate (Tanaka, first upper metallization pattern 12 and the first through electrode 13 of the inductive element 5, [0020], Figs. 1 and 2; Chen, second upper metallization pattern 142R is on the upper surface of the substrate 100, [0020], Figs. 1 and 11, [0021], Figs. 1 and 11).
Chen/Tanaka does not explicitly disclose a third through electrode connected to the second upper metallization pattern and in the substrate; a second lower metallization pattern connected to the third through electrode and on the lower surface of the substrate; a fourth through electrode connected to the second lower metallization pattern and in the substrate; and a third upper metallization pattern connected to the fourth through electrode and on the upper surface of the substrate.
However, Huang discloses wherein the inductive element (Huang, inductive element 110, [0057], Fig. 7) further comprises:
a second upper metallization pattern (second upper metallization pattern 116b within the first turn 112a, hereinafter, second upper metallization pattern 116b/a, [0028], Figs. 1 and 2) connected to the second through electrode (second upper metallization pattern 116b/a is connected to the second through electrode 108/ab of the second vertical segment 114b, [0028], Figs. 1 and 2) and on the upper surface of the substrate (second upper metallization pattern 116b/a is on the upper surface of the substrate 102/104, [0028], Figs. 1 and 2);
a third through electrode (second upper metallization pattern 116b/a is connected to the third through electrode 108/ba of the first vertical segment 114a within the second turn 112b, [0028], Figs. 1 and 2) connected to the second upper metallization pattern (second upper metallization pattern 116b/a is connected to the third through electrode 108/ba, [0028], Figs. 1 and 2) and in the substrate (second upper metallization pattern 116b/a is in the substrate 102/104, [0028], Figs. 1 and 2);
a second lower metallization pattern (second lower metallization pattern 116a/b, [0028, Figs. 1 and 2) connected to the third through electrode (second lower metallization pattern 116a/b is connected to the third through electrode 108/ba, [0028], Figs. 1 and 2) and on the lower surface of the substrate (second lower metallization pattern 116a/b is on the lower surface of the substrate 102/104, [0028, Figs. 1 and 2);
a fourth through electrode (fourth through electrode 108/cb of the third turn 112c and second vertical stack 114b, [0028], Figs. 1 and 2) connected to the second lower metallization pattern (fourth through electrode 108/cb is connected to the second lower metallization pattern 116a/b, [0028, Figs. 1 and 2) and in the substrate (fourth through electrode 108/cb is in the substrate 102/104, [0028], Figs. 1 and 2); and
a third upper metallization pattern (third upper metallization pattern 116b within the third turn 112c, hereinafter, third upper metallization pattern 116b/c, [0028], Figs. 1 and 2) connected to the fourth through electrode (third upper metallization pattern 116b/c is connected to the fourth through electrode 108/cb, [0028], Figs. 1 and 2) and on the upper surface of the substrate (third upper metallization pattern 116b/c is on the upper surface of the substrate 102/104, [0028], Figs. 1 and 2). The combination to utilize a plurality of metallization patterns and through electrodes allows for a winding structure to wind around a winding axis for the purpose of forming an inductor element, wherein by orienting the inductor to have turns that are arranged along vertical planes that intersect an underlying substrate, a size of the inductor can be decreased and issues affecting inductor performance can be mitigated (Huang, [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a plurality of metallization patterns and through electrodes to allow for a winding structure to wind around a winding axis for the purpose of forming an inductor element, wherein by orienting the inductor to have turns that are arranged along vertical planes that intersect an underlying substrate, a size of the inductor can be decreased and issues affecting inductor performance can be mitigated (Huang, [0019]).
Claim 26, Chen/Tanaka/Huang discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2; Huang, integrated circuit 100/200/700, [0021], Figs. 1, 2, and 7) of claim 23.
Chen/Tanaka/Huang discloses wherein the first, second, third and fourth through electrodes overlap each other in a second direction (first through electrode 108/aa, second through electrode 108/ab, third through electrode 108/ba and fourth through electrode 108/cb overlap each other in a second direction (i.e. X direction), [0057], Figs. 1 and 2), and
the second direction is parallel to the upper surface of the substrate and perpendicular to the first direction (second direction (i.e. X direction) is parallel to the upper surface of the substrate 102/104 and perpendicular to the first direction (i.e. Z direction), [0057], Figs. 1 and 2).
Claim 27, Chen/Tanaka discloses the integrated circuit (Chen, integrated circuit, [0018], Figs. 1 and 11; Tanaka, integrated circuit 1, [0018], Figs. 1 and 2) of claim 23.
Chen/Tanaka discloses wherein the second upper metallization pattern, the third upper metallization pattern, the first lower metallization pattern, and the second lower metallization pattern are parallel to the upper surface of the substrate (second upper metallization pattern 116b/a, the third upper metallization pattern 116b/c, the first lower metallization pattern 116a/a, and the second lower metallization pattern 116a/b are parallel to the upper surface of the substrate 102/104, [0057], Figs. 1 and 2) and extend in a second direction that is perpendicular to the first direction (second upper metallization pattern 116b/a, the third upper metallization pattern 116b/c, the first lower metallization pattern 116a/a, and the second lower metallization pattern 116a/b extend in a second direction (i.e. X direction) that is perpendicular to the first direction (i.e. Z direction), [0057], Figs. 1 and 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2019/0103354 A1) discloses an integrated circuit (integrated circuit 100, [0012], Fig. 1) comprising:
a first guard ring (first guard ring 107a, [0012], Fig. 1);
a second guard ring (second guard ring 109a, [0013], Fig. 1) spaced apart from the first guard ring 107a (second guard ring 109a is spaced apart from the first guard ring 107a, [0013], Fig. 1); and
an inductive element (inductive element 105, [0013], Fig. 1) between the first guard ring 107a and the second guard ring 109a (inductive element 105 is between the first guard ring 107a and the second guard ring 109a, [0013], Fig. 1).
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/CALVIN Y CHOI/Primary Patent Examiner, Art Unit 2812
