DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/321,851, application filed on 05/23/2023. Claims 1-18 are currently pending in this application.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 09/27/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1-8, 11-12 and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Oliver et al. (US PG Pub No. 2018/0013052).
7. With respect to independent claim 1, Oliver teaches:
A quantum chip (see quantum multi-chip module, Abstract; see system on chip, para 39; see qubit chip with multiple qbit chips on it, para 50-55), comprising:
a substrate (see substrate 240, para 231; see substrate of Fig 14);
M subchips (see at least 2 qubit chips 256a and 256b on multi-chip module of Fig 14, para 230-240), wherein each of the M subchips comprises N quantum bits (see n qubits, para 110), and the M subchips are spaced apart on a surface of the substrate (spacing between the first and second qubit chips, para 225);
a coupling structure (coupling superconducting circuits to substrate via superconducting bumps, para 30), configured to implement an interconnection between the M subchips (interconnection between chips, superconducting interconnects, para 30); and
a cavity mode suppression structure (gap capacitor, para 291; reducing coupling in spacing between superconductors, as gap capacitors, para 291; capacitors having appropriate spacing may be used, para 291; resonator in gap/cavity, para 156), disposed on an edge of each of the M subchips and/or in a gap between the M subchips (resonator suppression structure between edge of through line gap and edge of resonator gap, para 156), and configured to increase a cavity mode frequency of the quantum chip (see increasing quality factor of superconducting resonator, para 11),
wherein M is a positive integer greater than 1, and N is a positive integer greater than or equal to 1 (see M is at least 2 qubit chips, as shown in Fig 14; see n qubits, para 110).
8. With respect to claim 2, Oliver teaches:
wherein the coupling structure is a resonant cavity or a capacitor (gap capacitor, para 291; reducing coupling in spacing between superconductors, as gap capacitors, para 291; capacitors having appropriate spacing may be used, para 291; resonator in gap/cavity, para 156).
9. With respect to claim 3, Oliver teaches:
wherein the cavity mode suppression structure is disposed on the edge of each of the M subchips (gap capacitor, para 291; reducing coupling in spacing between superconductors, as gap capacitors, para 291; capacitors having appropriate spacing may be used, para 291; resonator in gap/cavity, para 156; resonator suppression structure between edge of through line gap and edge of resonator gap, para 156); and
a plurality of ground solder joints is disposed on edges of the M subchips, the plurality of ground solder joints is electrically connected to the substrate (coupling superconducting circuits to substrate via superconducting bumps, para 30), and
the plurality of ground solder joints constitute the cavity mode suppression structure (resonator suppression structure between edge of through line gap and edge of resonator gap, para 156; coupling superconducting circuits to substrate via superconducting bumps, para 30).
10. With respect to claim 4, Oliver teaches:
wherein the cavity mode suppression structure is disposed in the gap between the M subchips (gap capacitor, para 291; reducing coupling in spacing between superconductors, as gap capacitors, para 291; capacitors having appropriate spacing may be used, para 291; resonator in gap/cavity, para 156; resonator suppression structure between edge of through line gap and edge of resonator gap, para 156); and
the cavity mode suppression structure is a metal body or a solid structure, of which a surface is provided with a conductive layer (gap capacitor in conductive layer, para 291; reducing coupling in spacing between superconductors, as gap capacitors, para 291; resonator suppression structure between edge of through line gap and edge of resonator gap, para 156).
11. With respect to claim 5, Oliver teaches:
wherein the cavity mode suppression structure is an arc-shaped protrusion, a circular, an oval, a rectangular, or other polygonal column or block structure (see shaped protrusions on superconducting multi-chip structure, Fig 14).
12. With respect to claim 6, Oliver teaches:
wherein the M subchips are disposed in a rectangular array (see rectangular array of qubit chips in Fig 14).
13. With respect to claim 7, Oliver teaches:
wherein the coupling structure comprises a first coupling structure that is disposed between two adjacent subchips, and is configured to implement a connection between the two adjacent subchips (coupling superconducting circuits to substrate via superconducting bumps, para 30; interconnection between chips, superconducting interconnects, para 30).
14. With respect to claim 8, Oliver teaches:
wherein the coupling structure comprises a second coupling structure (see first and second coupling superconducting circuits to substrate via superconducting bumps, para 30; interconnection between chips, superconducting interconnects, para 30); and
the second coupling structure is disposed between two subchips disposed diagonally, and is configured to implement a connection between the two subchips disposed diagonally (see diagonal coupling structure 354c, Fig 19).
15. With respect to claim 11, Oliver teaches:
wherein the M subchips are disposed on the substrate in a flip-chip or wire bonding manner (see flip-chip, para 19; wirebonding, para 120).
16. With respect to claim 12, Oliver teaches:
a first electrode layer and a second electrode layer disposed on a surface of the substrate (see electrodes on layers of substrate surface, Fig 14).
17. With respect to independent claim 17, Oliver teaches:
A quantum computer (see quantum multi-chip module, Abstract; see system on chip, para 39; see qubit chip with multiple qbit chips on it, para 50-55), comprising a control system (bias control line, para 49; coupling control system, para 52), a low-temperature transmission system (see low temperature operation, para 25; microwave frequency ranges, para 25; refrigerator temperatures, para 111), and a quantum chip (see quantum multi-chip module, Abstract; see system on chip, para 39; see qubit chip with multiple qbit chips on it, para 50-55), wherein the quantum chip includes:
a substrate (see substrate 240, para 231; see substrate of Fig 14);
M subchips (see at least 2 qubit chips 256a and 256b on multi-chip module of Fig 14, para 230-240), wherein each of the M subchips comprises N quantum bits (see at least 2 qubit chips 256a and 256b on multi-chip module of Fig 14, para 230-240), and the M subchips are spaced apart on a surface of the substrate (spacing between the first and second qubit chips, para 225);
a coupling structure (coupling superconducting circuits to substrate via superconducting bumps, para 30), configured to implement an interconnection between the M subchips (interconnection between chips, superconducting interconnects, para 30); and
a cavity mode suppression structure (gap capacitor, para 291; reducing coupling in spacing between superconductors, as gap capacitors, para 291; capacitors having appropriate spacing may be used, para 291; resonator in gap/cavity, para 156), disposed on an edge of each of the M subchips and/or in a gap between the M subchips (resonator suppression structure between edge of through line gap and edge of resonator gap, para 156), and configured to increase a cavity mode frequency of the quantum chip (resonator suppression structure between edge of through line gap and edge of resonator gap, para 156),
wherein M is a positive integer greater than 1, and N is a positive integer greater than or equal to 1 (resonator suppression structure between edge of through line gap and edge of resonator gap, para 156), and
the control system transmits one or more signals to the quantum chip by using the low-temperature transmission system (see transmission in low temperature operation, para 25; microwave frequency ranges, para 25; refrigerator temperatures, para 111).
18. With respect to claim 18, Oliver teaches:
wherein the low-temperature transmission system comprises a refrigeration component and a low-temperature microwave circuit, the refrigeration component is configured to cool the low-temperature microwave circuit (see transmission in low temperature operation, para 25; microwave frequency ranges, para 25; refrigerator temperatures, para 111).
Allowable Subject Matter
19. Claims 9-10 and 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
20. With respect to claims 9-10, the prior art made of record fails to teach the combination of steps recited in claim 9, including the following particular combination of steps as recited in claim 9, as follows:
wherein the coupling structure comprises a first coupling structure and a second coupling structure; the first coupling structure is disposed between two adjacent subchips, and is configured to implement a connection between the two adjacent subchips; and the second coupling structure is disposed between two subchips disposed diagonally, and is configured to implement a connection between the two subchips disposed diagonally.
21. With respect to claim 13, the prior art made of record fails to teach the combination of steps recited in claim 13, including the following particular combination of steps as recited in claim 13, as follows:
wherein the first electrode layer is connected to a solder joint of one of the M subchips, to implement a connection between the first electrode layer and the subchip, and
the second electrode layer is connected to a solder joint of another one of the M subchips, to implement a connection between the second electrode layer and the other subchip.
22. With respect to claim 14, the prior art made of record fails to teach the combination of steps recited in claim 14, including the following particular combination of steps as recited in claim 14, as follows:
further comprises a third electrode layer disposed on an upper surface of the substrate, wherein the first electrode layer and the second electrode layer are disposed on a lower surface of the substrate, the substrate is used as a dielectric layer, and the first electrode layer, the second electrode layer, and the third electrode layer form a coupling capacitor.
23. With respect to claim 15, the prior art made of record fails to teach the combination of steps recited in claim 15, including the following particular combination of steps as recited in claim 15, as follows:
a dielectric layer formed on upper surfaces of the first electrode layer and the second electrode layer, and a third electrode layer formed on an upper surface of the dielectric layer, wherein the first electrode layer and the second electrode layer are disposed on an upper surface of the substrate, and the first electrode layer, the second electrode layer, the dielectric layer, and the third electrode layer form a coupling capacitor.
24. With respect to claim 16, the prior art made of record fails to teach the combination of steps recited in claim 16, including the following particular combination of steps as recited in claim 16, as follows:
a dielectric layer formed on upper surfaces of the first electrode layer and the second electrode layer, and a third electrode layer formed on an upper surface of the dielectric layer, wherein the first electrode layer and the second electrode layer are disposed on an upper surface of the substrate, and the first electrode layer, the second electrode layer, the dielectric layer, and the third electrode layer form a coupling capacitor.
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
Prosecution Insights