Attorney Docket Number: 2557-003900-US
Filing Date: 05/23/2023
Claimed Priority Date: 10/14/2022 (KR 10-2022-0132716)
Inventors: Kim et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 12/11/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 12/11/2025 in reply to the previous Office action mailed on 09/11/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-3 and 5-20.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: 102M.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because figure 20A includes the following reference character not mentioned in the description: VAE1.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because figure 21A includes the following reference character not mentioned in the description: VAE2.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon (US 2019/0115351).
Regarding claim 1, Jeon (see, e.g., fig. 4) shows all aspects of the instant invention, including an integrated circuit device comprising:
a first conductive pattern 230 on a substrate 100;
a second conductive pattern 220 surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern;
an upper insulating structure 210 on the first conductive pattern and the second conductive pattern; and
an upper conductive pattern 240 extending in a vertical direction through the upper insulating structure
wherein the upper conductive pattern 240 comprises:
a main plug portion overlapping the first conductive pattern 230 and the second conductive pattern 220 in the vertical direction;
a vertical extension portion extending from a local region of the main plug portion toward the substrate 100, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction; and
wherein:
the main plug portion fills a via hole (cavity shown in 210 filled by upper conductive pattern 240 and subsequently the main plug portion of 240) passing through the upper insulating structure 210 in the vertical direction; and
a first length from the substrate 100 to an uppermost surface of the first conductive pattern 230 in the vertical direction is greater than a second length from the substrate to an uppermost surface of the second conductive pattern 220 in the vertical direction (see, e.g., fig. 4 and pars.0046/ll.1-3 and 0047/ll.1-3)
Regarding claim 2, Jeon (see, e.g., fig. 4) shows that:
the first conductive pattern 230 comprises a top portion protruding more than the second conductive pattern 220 in a direction away from the substrate 100; and
the top portion of the first conductive pattern 230 is in a space defined by the vertical extension portion
Regarding claim 3, Jeon (see, e.g., pars.0024/ll.25-27 and 0025/ll.4-7) shows that a constituent material (e.g., aluminum) of the upper conductive pattern 240 has a resistivity less than a resistivity of a constituent material (e.g., titanium) of the second conductive pattern 220.
Regarding claim 7, Jeon (see, e.g., fig. 7) shows that in the vertical direction a length of the second conductive pattern 220 is less than a length of the first conductive pattern 230.
Regarding claim 10, Jeon (see, e.g., fig. 4) shows that the upper conductive pattern 240 is in contact with at least a portion of each of the first conductive pattern 230 and the second conductive pattern 220.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Chung (US 2019/0393318).
Regarding claim 1, Jeon (see, e.g., fig. 4) shows most or all aspects of the instant invention, including an integrated circuit device comprising:
a first conductive pattern 230 on a substrate 100;
a second conductive pattern 220 surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern;
an upper insulating structure 210 on the first conductive pattern and the second conductive pattern; and
an upper conductive pattern 240 extending in a vertical direction through the upper insulating structure;
wherein the upper conductive pattern 240 comprises:
a main plug portion overlapping the first conductive pattern 230 and the second conductive pattern 220 in the vertical direction;
a vertical extension portion extending from a local region of the main plug portion toward the substrate 100, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction; and
wherein:
the main plug portion fills a via hole (cavity shown in 210 filled by upper conductive pattern 240 and subsequently the main plug portion of 240) passing through the upper insulating structure 210 in the vertical direction; and
a first length from the substrate 100 to an uppermost surface of the first conductive pattern 230 in the vertical direction is greater than a second length from the substrate to an uppermost surface of the second conductive pattern 220 in the vertical direction (see, e.g., pars.0046/ll.1-3 and 0047/ll.1-3)
Jeon shows most or all aspects of the instant invention, and further shows that a first length from the substrate 100 to an uppermost surface of the first conductive pattern 230 in the vertical direction is greater than a second length from the substrate to an uppermost surface of the second conductive pattern 220 in the vertical direction (see, e.g., fig. 4 and pars.0046/ll.1-3 and 0047/ll.1-3). Furthermore, Chung, in the same field of endeavor and in a similar device to Jeon, teaches a variety of integrated circuit device embodiments showing a variety of first and second lengths, including an embodiment wherein a first length from a substrate 100 to an uppermost surface of a first conductive pattern FM1 is explicitly greater than a second length from the substrate to an uppermost surface of a second conductive pattern BM1 in a vertical direction (see, e.g., Chung: figs. 2A and 17 and par.0075/ll.1-4). Chung teaches that the integrated circuit device embodiment wherein a first length from the substrate to an uppermost surface of the first conductive pattern in the vertical direction is explicitly greater than a second length from the substrate to an uppermost surface of the second conductive pattern in the vertical direction functions equivalently to other integrated circuit device embodiments possessing different first and second lengths, including but not limited to integrated circuit device embodiments wherein the second length is greater than or equal to the first length (see, e.g., Chung: figs. 2A and 15-19 and par.0072).
Chung is evidence showing that one of ordinary skill in the art would appreciate that a first length from the substrate to an uppermost surface of the first conductive pattern in the vertical direction being greater than a second length from the substrate to an uppermost surface of the second conductive pattern in the vertical direction would be equivalent to a first length from the substrate to an uppermost surface of the first conductive pattern in the vertical direction having another relation to a second length from the substrate to an uppermost surface of the second conductive pattern in the vertical direction, and that such differences would result in no unexpected changes in the performance of the integrated circuit device of Jeon. That is, the first and second lengths of both Jeon and Chung’s device embodiment or Chung’s other device embodiments would yield the predictable result of providing suitably-sized conductive structures capable of mechanical and electrical integration with other conductive structures in an integrated circuit device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first length from the substrate to an uppermost surface of the first conductive pattern in the vertical direction be greater than a second length from the substrate to an uppermost surface of the second conductive pattern in the vertical direction, as taught by Jeon and Chung, or a first length from the substrate to an uppermost surface of the first conductive pattern in the vertical direction have another relation to a second length from the substrate to an uppermost surface of the second conductive pattern in the vertical direction, as taught by Chung’s other embodiments, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably-sized conductive structures capable of mechanical and electrical integration with other conductive structures in an integrated circuit device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Regarding claim 2, Jeon (see, e.g., fig. 4) shows that:
the first conductive pattern 230 comprises a top portion protruding more than the second conductive pattern 220 in a direction away from the substrate 100; and
the top portion of the first conductive pattern 230 is in a space defined by the vertical extension portion
Regarding claim 3, Jeon (see, e.g., pars.0024/ll.25-27 and 0025/ll.4-7) shows that a constituent material (e.g., aluminum) of the upper conductive pattern 240 has a resistivity less than a resistivity of a constituent material (e.g., titanium) of the second conductive pattern 220.
Regarding claim 7, Jeon (see, e.g., fig. 7) shows that in the vertical direction a length of the second conductive pattern 220 is less than a length of the first conductive pattern 230.
Regarding claim 10, Jeon (see, e.g., fig. 4) shows that the upper conductive pattern 240 is in contact with at least a portion of each of the first conductive pattern 230 and the second conductive pattern 220.
Claims 1, 5-8, and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Lin (US 2021/0098376).
Regarding claim 1, Chung (see, e.g., figs. 17 and 2A) shows most aspects of the instant invention, including an integrated circuit device comprising:
a first conductive pattern FM1 on a substrate 100;
a second conductive pattern BM1 surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern;
an upper insulating structure 120 on the first conductive pattern and the second conductive pattern; and
an upper conductive pattern CT2 extending in a vertical direction through the upper insulating structure
wherein:
the upper conductive pattern CT2 fills a via hole (cavity in 120 filled by CT2) passing through the upper insulating structure 120 in the vertical direction; and
a first length from the substrate 100 to an uppermost surface of the first conductive pattern FM1 is greater than a second length from the substrate to an uppermost surface of the second conductive pattern BM1 in the vertical direction (see, e.g., par.0075/ll.1-4)
Although Chung shows most aspects of the instant invention, Chung fails to show that the upper conductive pattern comprises a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction and a vertical extension portion extending from a local region of the main plug towards the substrate, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern. Additionally, although Chung teaches that Chung’s upper conductive pattern fills a via hole passing through the upper insulating structure in the vertical direction, Chung fails to specify that a main plug portion (which would be included in the upper conductive pattern) fills a via hole passing through the upper insulating structure in the vertical direction.
Lin, in a similar device and in the same field of endeavor, shows many aspects of Chung’s device listed above and further shows an upper conductive pattern 350B comprising a main plug portion overlapping a first conductive pattern 286 and a second conductive pattern 284 in the vertical direction and a vertical extension portion extending from a local region of the main plug towards a substrate 210, the vertical extension portion covering an upper portion of the first conductive pattern and overlapping the second conductive pattern in the vertical direction, and the main plug portion filling a via hole 300B passing through an upper insulating structure 254/294/292 (see, e.g., Lin: figs. 1A-1B, 7A, and 16). Lin teaches the importance of increasing the contact area between an upper conductive pattern and first and second conductive patterns, wherein increasing the contact area improves the structural integrity of the upper conductive pattern, reduces resistance between the upper conductive pattern and first and second conductive patterns, and improves the overall performance of the integrated circuit device (see, e.g., Lin: pars.0037/ll.35-38 and 0047/ll.20-24). Lin further teaches that increasing the contact area between first and second conductive patterns and upper conductive pattern can be done through the etching and removing of material (see, e.g., Lin: par.0037/ll.35-38). Additionally, Lin teaches that having a main plug portion filling a via hole passing through an upper insulating layer in a vertical direction allows manipulation of sizing of the via hole, which can prevent or minimize formation of gaps when filling the via holes, thereby significantly decreasing contact resistance of the formed upper conductive pattern and subsequent main plug portion (see, e.g., Lin: pars.0033/ll.27-35 and 41-45).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chung’s upper conductive pattern CT2 extend in the place of Chung’s insulation layer MIL, thus forming a main plug and vertical extension portion as claimed, so as to increase the contact area between Chung’s upper conductive pattern and first and second conductive patterns, as taught by Lin, to subsequently improve the structural integrity of Chung’s upper conductive pattern, reduce resistance between Chung’s first and second conductive patterns and upper conductive pattern, and improve the overall performance of Chung’s integrated circuit device.
Accordingly, since Chung teaches that Chung’s upper conductive pattern CT2 fills a via hole (cavity in 120 filled by CT2) passing through Chung’s upper insulating structure 120 in the vertical direction, it would be apparent that an upper conductive pattern comprising a “main plug portion”, as taught by Lin, would subsequently necessarily teach the limitation “wherein the main plug portion fills a via hole passing through the upper insulating structure in the vertical direction”, wherein “wherein the upper conductive structure fills a via hole…” is replaced by “wherein the main plug portion fills a via hole…”, as taught by Lin. Furthermore, Lin is evidence that it would have been obvious at the time of filing the invention that one of ordinary skill in the art would have particular incentive to have a main plug portion filling a via hole passing through an upper insulating structure in the vertical direction in the device of Chung, as taught by Lin, so as form a structure allowing manipulation of the via hole sizing, thereby preventing or minimizing formation of gaps when filling the via holes and significantly decreasing contact resistance of the main plug portion in Chung’s device.
Regarding claim 12, Chung (see, e.g., figs. 17 and 2A) shows most aspects of the instant invention, including an integrated circuit device comprising:
a fin-type active region AP1 protruding upward from a substrate 100;
a source/drain region SD1 on the fin-type active region;
a gate line GE/GI/GS on the fin-type active region and extending in a direction intersecting the fin-type active region;
an insulating structure CSP on the source/drain region;
a source/drain contact CT1 passing through the insulating structure in a vertical direction and connected to the source/drain region;
an upper insulating structure 120 on each of the source drain contact and the gate line;
a first upper conductive pattern CT2 passing through the upper insulating structure in the vertical direction and connected to the source/drain contact; and
a second upper conductive pattern GC passing through the upper insulating structure in the vertical direction and connected to the gate line;
wherein:
at least one of the source/drain contact CT1 and the gate line GE/GI/GS comprises a first conductive pattern FM1 and a second conductive pattern BM1, the second conductive pattern surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern;
at least one of the first upper conductive pattern CT2 and the second upper conductive pattern GC fills a via hole (cavity in 120 filled by CT2 or GC) passing through the upper insulating structure 120 in the vertical direction; and
a first length from the substrate 100 to an uppermost surface of the first conductive pattern FM1 is greater than a second length from the substrate to an uppermost surface of the second conductive pattern BM1 in the vertical direction (see, e.g., par.0075/ll.1-4)
Although Chung shows most aspects of the instant invention, Chung fails to specify that at least one of Chung’s first upper conductive pattern CT2 and second upper conductive pattern GC comprises a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction and a vertical extension portion extending from a local region of the main plug portion toward the substrate, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction. For example, Chung fails to show that the first upper conductive pattern CT2 comprises a main plug portion overlapping the first conductive pattern FM1 and the second conductive pattern BM1 in the vertical direction and a vertical extension portion extending from a local region of the main plug portion toward the substrate 100, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction. Additionally, although Chung teaches that Chung’s first upper conductive pattern fills a via hole passing through the upper insulating structure in the vertical direction, Chung fails to specify that a main plug portion (which would be included in the first upper conductive pattern) fills a via hole passing through the upper insulating structure in the vertical direction.
Lin, in a similar device to Chung and showing many of the claimed features listed above in paragraph 30, teaches that forming a structure having first and second conductive patterns in greater contact with a first upper conductive pattern improves the structural integrity of the upper conductive pattern, reduces resistance between the upper conductive pattern and first and second conductive patterns, and improves the overall performance of an integrated circuit device (see, e.g., Lin: fig. 16 and pars.0037/ll.35-38 and 0047/ll.20-24). Lin further teaches that increasing the contact area between first and second conductive patterns and upper conductive pattern can be done through the etching and removing of material (see, e.g., Lin: par.0037/ll.35-38). Additionally, Lin teaches that having a main plug portion filling a via hole passing through an upper insulating layer in a vertical direction allows manipulation of sizing of the via hole, which can prevent or minimize formation of gaps when filling the via holes, thereby significantly decreasing contact resistance of the formed upper conductive pattern and subsequent main plug portion (see, e.g., Lin: pars.0033/ll.27-35 and 41-45). See the comments stated above in paragraphs 25-29 with respect to claim 1, which are considered to be repeated here.
Regarding claim 5, Chung (see, e.g., fig. 2A and par.0028/ll.1-4) shows:
a source/drain region SD1 between the substrate 100 and the first conductive pattern FM1
wherein:
the first conductive pattern FM1 and the second conductive pattern BM1 are each electrically connected to the source/drain region
Regarding claim 6, Chung (see, e.g., fig. 2A and pars. 0032/ll.1-4) shows:
a source/drain region SD1 between the substrate 100 and the first conductive pattern FM1
wherein:
the first conductive pattern FM1 comprises a material copper (Cu); and
the second conductive pattern comprises a metal nitride
Regarding claim 7, Chung (see, e.g., fig. 17 and par.0075/ll.1-4) shows that in the vertical direction a length of the second conductive pattern BM1 is less than a length of the first conductive pattern FM1.
Regarding claim 8, Chung (see, e.g., figs. 17 and 2A and par.0025/ll.5-7) shows:
a channel region CH1 between the substrate 100 and the second conductive pattern BM1; and
a gate dielectric film GI between the channel region and the second conductive pattern
wherein:
the first conductive pattern FM1 is apart from the channel region CH1 with the gate dielectric film GI and the second conductive pattern BM1 between the first conductive pattern and the channel region
Regarding claim 11, Chung (see, e.g., par.0032/ll.5-7) shows that the upper conductive pattern CT2 comprises at least one of molybdenum (Mo) or tungsten (W).
Regarding claim 13, Chung (see, e.g., pars.0032/ll.1-7 and 0037/ll.1-3) shows that a constituent material of each of the first upper conductive pattern CT2 (e.g., Mo) and the second upper conductive pattern GC (e.g., W) has a resistivity less than a resistivity of a constituent material (e.g., titanium) of the second conductive pattern BM1.
Regarding claim 14, Chung (see, e.g., figs. 17 and 2A, par.0032/ll.1-7) shows that:
the first upper conductive pattern CT2 comprises the main plug portion and the vertical extension portion (see paragraphs 30-32 stated above);
the first conductive pattern FM1 comprises a material Cu;
the second conductive pattern BM1 comprises a metal nitride; and
the first upper conductive pattern comprises Mo or W
Furthermore, Lin (see, e.g., Lin: figs. 7A, 8A, and 16) shows that the main plug portion and via extension portion of the first upper conductive pattern 350B are integrally connected to each other and comprise a same material.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon or Jeon/Chung in view of Bae (US 2021/0384192).
Regarding claim 9, Jeon and Jeon/Chung shows most aspects of the instant invention (see paragraphs 9 and 16-19 above). Furthermore, although Jeon shows that a channel region is below Jeon’s second conductive pattern 220 (see, e.g., par.0040/ll.6-7), that Jeon’s first conductive pattern 230 comprises TiN (see, e.g., par.0023/ll.9-13), and that Jeon’s second conductive pattern may comprise titanium (e.g., in titanium nitride) (see, e.g., 18-20), Jeon fails to specify that the channel region is between the substrate 100 and the second conductive pattern and that the second conductive pattern comprises TiAlC. Bae, in a similar device to Jeon and in the same field of endeavor, teaches that having a channel regions NSS between a substrate 902 and a conductive pattern 960M forms transistors (see, e.g., Bae: fig. 31 and par.0091/ll.9-11). Bae further teaches TiAlC to be suitable material for conductive patterns, and titanium nitride and TiAlC to be equivalent for their use as conductive patterns (see, e.g., Bae: pars.0038/ll.11-14 and 0096/ll.15-20).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Jeon’s channel region between Jeon’s substrate and second conductive pattern, as taught by Bae, so as to form transistors, thus expanding the regulation of electric current flow in Jeon’s device. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use TiAlC in Jeon’s second conductive pattern, as taught by Bae, or to use titanium nitride, as taught by Jeon, because these materials were recognized in the semiconductor art as equivalents for their use as conductive pattern materials, and selecting among known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Huang (US 11,444,200) and Lin.
Regarding claim 17, Chung (see, e.g., figs. 17 and 2A) shows most aspects of the instant invention, including an integrated circuit device comprising:
a fin-type active region AP1 on a substrate 100 and extending lengthwise in a first horizontal direction;
at least one channel region CH1 over the fin-type active region;
a source/drain region SD1 facing the at least one channel region in the first horizontal direction;
a gate line GE/GI/GS on the fin-type active region and extending lengthwise in a second horizontal direction that intersects the first horizontal direction;
a source/drain contact CT1 connected to the source/drain region;
an upper insulating structure 120 on the source/drain contact and the gate line;
a via contact CT2 connected to the source/drain contact, the via contact extending in a vertical direction through the upper insulating structure; and
a gate contact GC connected to the gate line, the gate contact extending in the vertical direction through the upper insulating structure
wherein:
the source/drain contact CT1 comprises a contact plug FM1 and a conductive barrier pattern BM1 that surrounds a portion of the contact plug and covers a lower portion of a sidewall of the contact plug;
the via contact CT2 fills a via hole (cavity in 120 filled by CT2) passing through the upper insulating structure 120 in the vertical direction; and
a first length from the substrate 100 to an uppermost surface of the contact plug FM1 of the source/drain contact CT1 is greater than a second length from the substrate to an uppermost surface of the conductive barrier pattern BM1 of the source/drain contact in the vertical direction (see, e.g., par.0075/ll.1-4)
Although Chung shows most aspects of the instant invention, Chung fails to specify that the channel region CH1 comprises at least one nanosheet, that the gate line surrounds the at least one nanosheet, and that the via contact comprises a first main plug portion overlapping the contact plug and the conductive barrier in a vertical direction and a first vertical extension portion extending from a local region of the first main plug toward the substrate, the first vertical extension covering an upper portion of the sidewall of the contact plug and overlapping the conductive barrier pattern in the vertical direction. Additionally, although Chung teaches that Chung’s via contact CT2 fills a via hole passing through the upper insulating structure 120 in the vertical direction, Chung fails to specify that a first main plug portion (which would be included in the via contact) fills a via hole passing through the upper insulating structure in the vertical direction.
Regarding the channel region, Huang, in the same field of endeavor and in a similar device to Chung, teaches that having a channel region comprising at least one nanosheet with a gate line surrounding the at least one nanosheet results forms gate-all around transistors, which can be aggressively scaled-down while maintaining gate control and mitigating short-channel effects (see, e.g., Huang: background/ll.16-27 and col.3/ll.18-20).
Regarding the via contact, Lin, in a similar device and in the same field of endeavor, shows many aspects of Chung’s device listed above and further shows a via contact 350B comprising a first main plug portion overlapping a contact plug 286 and a conductive barrier pattern 284 in a vertical direction and a first vertical extension portion extending from a local region of the first main plug towards a substrate 210, the first vertical extension portion covering an upper portion of the contact plug and overlapping the conductive barrier pattern in the vertical direction (see, e.g., Lin: fig. 16). Lin teaches the importance of increasing the contact area between a via contact and contact plug and conductive barrier pattern, wherein increasing the contact area improves the structural integrity of the via contact, reduces resistance between the via contact and contact plug/conductive barrier pattern, and improves the overall performance of the integrated circuit device (see, e.g., Lin: pars.0037/ll.35-38 and 0047/ll.20-24). Lin further teaches that increasing the contact area between a contact plug/conductive barrier pattern and a via contact can be done through the etching and removing of material (see, e.g., Lin: par.0037/ll.35-38). Additionally, Lin teaches that having a first main plug portion filling a via hole passing through an upper insulating layer in a vertical direction allows manipulation of sizing of the via hole, which can prevent or minimize formation of gaps when filling the via holes, thereby significantly decreasing contact resistance of the formed via contact and subsequent first main plug portion (see, e.g., Lin: pars.0033/ll.27-35 and 41-45).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chung’s channel region comprise at least one nanosheet with the gate line surrounding the at least one nanosheet, as taught by Huang, so as to form a transistor device that promotes miniaturization while maintaining gate control and mitigating short-channel effects. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chung’s via contact CT2 extend in the place of Chung’s insulation layer MIL, thus forming a first main plug and first vertical extension portion as claimed, so as to increase the contact area between Chung’s via contact and contact plug and conductive barrier pattern, as taught by Lin, to subsequently improve the structural integrity of Chung’s via contact, reduce resistance between Chung’s via contact and contact plug/conductive barrier pattern, and improve the overall performance of Chung’s integrated circuit device.
Accordingly, since Chung teaches that Chung’s via contact CT2 fills a via hole (cavity in 120 filled by CT2) passing through Chung’s upper insulating structure 120 in the vertical direction, it would be apparent that a via contact comprising a “first main plug portion”, as taught by Lin, would subsequently necessarily teach the limitation “wherein the first main plug portion fills a via hole passing through the upper insulating structure in the vertical direction”, wherein “wherein the via contact fills a via hole…” is replaced by “wherein the first main plug portion fills a via hole…”, as taught by Lin. Furthermore, Lin is evidence that it would have been obvious at the time of filing the invention that one of ordinary skill in the art would have particular incentive to have a first main plug portion filling a via hole passing through an upper insulating structure in the vertical direction in the device of Chung, as taught by Lin, so as form a structure allowing manipulation of the via hole sizing, thereby preventing or minimizing formation of gaps when filling the via holes and significantly decreasing contact resistance of the first main plug portion in Chung’s device.
Regarding claim 16, Chung/Lin shows most aspects of the instant invention (see paragraphs 30-32 above). Chung (see, e.g., figs. 17 and 2A) further specifies that a channel region CH1 exists between Chung’s fin-type active region and Chung’s gate line GE/GI/GS. However, Chung fails to specify that Chung’s channel region comprises at least one nanosheet surrounded by the gate line.
Huang, in the same field of endeavor and in a similar device to Chung, teaches that having a channel region comprising at least one nanosheet with a gate line surrounding the at least one nanosheet forms gate-all around transistors, which can be aggressively scaled-down while maintaining gate control and mitigating short-channel effects (see, e.g., Huang: background/ll.16-27 and col.3/ll.18-20).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chung’s channel region comprise at least one nanosheet with the gate line surrounding the at least one nanosheet, as taught by Huang, so as to form a transistor device that promotes miniaturization while maintaining gate control and mitigating short-channel effects.
Regarding claim 18, Chung (see, e.g., fig. 17) shows:
in the source/drain contact CT1, a length of the conductive barrier pattern BM1 in the vertical direction is less than a length of the contact plug FM1 in the vertical direction;
the first vertical extension portion of the via contact CT2 is in contact with an upper surface of the conductive barrier pattern (see the comments stated above paragraphs 45-49 above regarding the via contact, which are considered to be repeated here); and
a constituent material of each of the via contact CT2 (e.g., Mo) has a resistivity less than a resistivity of a constituent material (e.g., titanium) of the conductive barrier pattern BM1 (see, e.g., pars.0032/ll.1-7)
Furthermore, Lin (see, e.g., fig. 16) shows that the first vertical extension portion of the via contact 350B is in contact with an upper surface of the conductive barrier portion 284.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chung/Huang/Lin in view of Jeon.
Regarding claim 19, Chung/Huang/Lin shows most aspects of the instant invention (see paragraphs 45-50 above). Furthermore, Chung (see, e.g., figs. 17 and 2A) shows that the gate line contains a first metal-containing film GE arranged above the at least one nanosheet CH1 (see paragraphs 45-50 above regarding the channel region). Chung further teaches that the gate contact GC comprises a second main plug portion BM2 overlapping the first metal-containing film in the vertical direction. However, Chung/Huang/Lin fails to specify that the first metal-containing film is a work function metal-containing film, that the gate line comprises a second work function metal-containing film which surrounds a portion of the first work function metal-containing film and covers a lower portion of a sidewall of the first work function metal-containing film, and that the gate contact comprises a second vertical extension portion extending from a local region of the second main plug portion toward the substrate covering an upper portion of the sidewall of the first work function metal-containing film and overlapping the second work function metal-containing film in the vertical direction.
Jeon, in a similar device to Chung/Huang/Lin and in the same field of endeavor, teaches a gate line 230, 220 comprising a first work function metal-containing film 230 and a second work function metal-containing film 220 (see, e.g., par.0040/ll.13-15), wherein the second work function metal-containing film covers a lower portion of a sidewall of the first work function metal-containing film (see, e.g., Jeon: fig. 4). Jeon further teaches a gate contact 240 on the gate line comprising a second main plug portion overlapping the first and second work function metal-containing films in the vertical direction and a second vertical extension portion extending from a local region of the second main plug toward a substrate 100 covering an upper portion of the sidewall of the first work function metal-containing film and overlapping the second work function metal-containing film in the vertical direction. Jeon teaches that this shape and structure allows the gate contact 240 to act as a barrier, preventing gate induced drain leakage current between the gate line and the source/drain regions (see, e.g., Jeon: par.0047/ll.1-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include Jeon’s gate line and contact in Chung’s device, that is, to amend Chung’s gate line to comprise a first work function metal-containing film and a second work function metal-containing film, which surrounds a portion of the first work function metal-containing film and covers a lower portion of a sidewall of the first work function metal-containing film, as taught by Jeon, and to amend Chung’s gate contact to comprise Jeon’s second main plug portion overlapping the first and second work function metal-containing films in the vertical direction and second vertical extension portion extending from a local region of the second main plug portion toward the substrate covering an upper portion of the sidewall of the first work function metal-containing film and overlapping the second work function metal-containing film, so as to allow Chung’s gate contact to continue as a via structure electrically connected to other elements of Chung’s device while allowing the gate contact to simultaneously act as a barrier, preventing gate induced drain leakage current between Chung’s gate line and source/drain regions.
Regarding claim 20, Chung/Huang/Lin shows that the gate line is over at least one nanosheet (see paragraphs 45-50 above regarding the channel region).
Furthermore, Jeon teaches that in the gate line, a length of the second work function metal-containing film 220 in the vertical direction is less than a length of the first work function metal-containing film 230 in the vertical direction (see, e.g., Jeon: fig. 4). Jeon also shows that the second vertical extension portion of the gate contact 240 is in contact with an upper surface of the second work function metal-containing film 220 (see, e.g., Jeon: fig. 4). Jeon (see, e.g., Jeon: pars.0022/ll.18-20 and 0025/ll.4-7) further shows that a constituent material (e.g., aluminum) of the gate contact 240 has a resistivity less than a resistivity of a constituent material (e.g., titanium) of the second work function metal-containing film 220.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chung/Lin in view of Jeon and Bae.
Regarding claim 15, Chung/Lin shows most aspects of the instant invention (see paragraphs 30-32 above). Chung (see, e.g., figs. 17 and 2A and pars.0032/ll.3-5 and 0037/ll.2-3) further shows that the second upper conductive pattern GC comprises a main plug portion overlapping a first conductive pattern GE of a gate line and that the second upper conductive pattern comprises Mo or W. However, Chung fails to specify that the second upper conductive pattern comprises a main plug portion overlapping a first conductive pattern and second conductive pattern in a vertical direction, wherein the main plug portion and the vertical extension portion are integrally connected to each other and comprise a same material, and that the first conductive pattern comprises TiN and the second conductive pattern comprises TiAlC.
Jeon, in a similar device to Chung/Huang/Lin and in the same field of endeavor, teaches a device comprising a first conductive pattern 230 and a second conductive pattern 220 akin to Chung (see, e.g., Jeon: fig. 4). Jeon further teaches a second upper conductive pattern 240 on the first and second conductive patterns, wherein the second upper conductive pattern comprises a second main plug portion overlapping the first and second conductive patterns in the vertical direction and a vertical extension portion extending from a local region of the main plug portion towards a substrate 100, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction, and wherein the main plug portion and the vertical extension portion are integrally connected to each other and comprise a same material (see, e.g., Jeon: fig. 4). Jeon teaches that this shape and structure allows the second upper conductive pattern 240 to act as a barrier, preventing gate induced drain leakage current between the gate line and the source/drain regions (see, e.g., Jeon: par.0047/ll.1-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include Jeon’s first and second conductive patterns and second upper conductive pattern in Chung’s device, that is, to amend Chung’s gate line to comprise first and second conductive patterns, as taught by Jeon, and to amend Chung’s second upper conductive pattern to comprise Jeon’s integrally-connected and same-material-comprising main plug portion overlapping the first and second conductive patterns in the vertical direction and vertical extension portion extending from a local region of the main plug portion toward the substrate covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern, so as to allow Chung’s second upper conductive pattern to continue as a via structure electrically connecting Chung’s gate line to other elements of Chung’s device while allowing the second upper conductive pattern to simultaneously act as a barrier, preventing gate induced drain leakage current between Chung’s gate line and source/drain regions.
Furthermore, although Jeon teaches that Jeon’s first conductive pattern 230 comprises TiN (see, e.g., par.0023/ll.9-13), and that Jeon’s second conductive pattern may comprise titanium (e.g., in titanium nitride) (see, e.g., 18-20), Jeon fails to specify that the second conductive pattern comprises TiAlC. Bae, in a similar device to Jeon, teaches TiAlC to be suitable material for conductive patterns, and titanium nitride and TiAlC to be equivalent for their use as conductive patterns (see, e.g, Bae: pars.0038/ll.11-14 and 0096/ll.15-20).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use TiAlC in Jeon’s second conductive pattern, as taught by Bae, or to use another titanium nitride, as taught by Jeon, because these materials were recognized in the semiconductor art as equivalents for their use as conductive pattern materials, and selecting among known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Response to Arguments
With respect to the drawings, Applicant argues that the present amendments filed on 12/11/2025 have overcome the objections to the drawings put forth in the previous Office action mailed on 09/11/2025. However, Applicant’s present amendments do not appear to include any amendments to the drawings and/or specification, including any amendments to the drawings and/or specification that render moot the objections to the drawings put forth in the previous Office action. Accordingly, the objections to the drawings put forth in the previous Office action are maintained.
With respect to the claims, Applicant argues:
As to independent claim 1, Applicants note that Jeon fails to disclose or suggest at least features such as “the main plug portion fills a via hole passing through the upper insulating structure in the vertical direction”. As to claims 1 and 12, none of the references are shown to disclose or suggest at least features such as “a first length from the substrate to an uppermost surface of the first conductive pattern in the vertical direction is greater than a second length from the substrate to an uppermost surface of the second conductive pattern in the vertical direction”. As to claim 17, none of the applied art has been shown to disclose or suggest at least features such as “a first length from the substrate to an uppermost surface of the contact plug of the source/drain contact in the vertical direction is greater than a second length from the substrate to an uppermost surface of the conductive barrier pattern of the source/drain contact in the vertical direction”.
The examiner responds:
With regards to independent claim 1, Jeon shows these features of the claimed invention. See, for example, figure 4 of Jeon, wherein a cavity shown in upper insulating structure 210 is filled by upper conductive pattern 240 and subsequently the main plug portion of 240, wherein the main plug portion then proceeds to mechanically and electrically connect to other conductive elements of Jeon’s device in the vertical direction (see, e.g., par.0038/ll.5-8). Accordingly, such a cavity constitutes a “via hole” as recited in the claim, and the comments reciting this “via hole” feature are considered to be repeated for other references recited in this Office action. Furthermore, with regards to independent claims 1 and 12 the references do disclose the recited “a first length from the substrate to an uppermost surface of the first conductive pattern in the vertical direction is greater than a second length from the substrate to an uppermost surface of the second conductive pattern in the vertical direction” feature of the claimed invention. See, for example, figures 2A and 17 and par.0075/ll.1-4 of Chung, wherein Chung discloses that a first length from a substrate 100 to an uppermost surface of a first conductive pattern FM1 is explicitly greater than a second length from the substrate to an uppermost surface of a second conductive pattern BM1 in a vertical direction. Similarly, with regards to independent claim 17, Chung (see, e.g., figs. 2A and 17 and par.0075/ll.1-4) discloses that a first length from the substrate 100 to an uppermost surface of the contact plug FM1 of the source/drain contact CT1 is greater than a second length from the substrate to an uppermost surface of the conductive barrier pattern BM1 of the source/drain contact in the vertical direction.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814